PLC810PG Datasheet, PDF (5/26 Pages) Power Integrations, Inc. – Continuous Mode PFC & LLC Controller Continuous Mode PFC & LLC Controller

PLC810PG
ISP (3)
VCOMP (1)
FBP (23)
GND (2,19)
FBL (20)
FMAX (21)
V_{OC -}
+
OC FAULT
INVERSION
DVGA
and LPF
LLC CLOCK
PWM
+
OTA
V_FBPREF ^-
PHASE
ALIGNMENT
+
V_OVH
-
OV FAULT
UVLO
V_REF
V_IN(H)/V_{IN(L) +}
-
V_SD(H)V_SD(L)
+
-
PFC INHIBIT
INTERNAL REFERENCE
GENERATOR
LLC OFF
SOFT ^{ONE SHOT}
START ⁴⁰⁹⁶
CYCLES
OVL FAULT
LLC CURRENT
FEEDBACK
RAMP AND CLOCK
GENERATOR
DEAD TIME
GENERATOR
NON-
OVERLAP
GENERATOR
ISL (22)
+
1.2 V -
CLAMP
+
V_ISL(F)V_ISL(S)
-
CLAMP
LLC OFF
OVL FAULT
LLC FAULT
RESET
V_UVLO(+)
V_UVLO(-)
(6) GATEP
(7) VCC
(8) GNDP
3.3 V LINEAR
REGULATOR
(4) VREF
(13) VCCHB
(12) GATEH
(14) HB
(16) VCCL
(10) GATEL
(9) GNDL
Figure 3. Block Diagram of PLC810PG. Reserved Pins are not Shown.
PI-5041-112608
Block Diagram
Figure 3 shows a block diagram of the functional elements that
make up the PLC810PG. The reserved pins are not shown in
the diagram. Those pins are reserved for PI use during
manufacture and testing. The PLC810PG PFC control blocks
and circuits are shown on the upper half of the block diagram,
while the LLC control blocks are shown on the lower half. Some
of the functional blocks are shared.
PLC810PG Power Block
The PLC810PG is powered through VCC and VCCL pins. The
VCCL pin powers the LLC driver while VCC powers the rest of the
device. VCC pin must be supplied by a voltage between V_UVLO(+)
and 15 V. The provided supply is continuously compared against
the V_UVLO(+) and V_UVLO(-) thresholds to start/stop the PLC810PG.
When VCC is above the V_UVLO(+) threshold the PLC810PG de-
asserts the undervoltage lockout (UVLO) signal allowing the device
to start. If VCC falls below V_UVLO(-), the UVLO signal is asserted,
shutting down the PLC810PG.
The VCCL pin powers the LLC driver, and VCCHB provides the
charge for the LLC high-side MOSFET for gate drive.
An internal linear regulator is used to generate a 3.3 V rail to power
the low voltage circuits inside the PLC810PG. The 3.3 V is brought
outside on the VREF pin allowing external low voltage circuits to be
powered by the PLC810PG.
www.powerint.com
5
Rev. F 08/09