PLC810PG Datasheet, PDF (14/26 Pages) Power Integrations, Inc. – Continuous Mode PFC & LLC Controller Continuous Mode PFC & LLC Controller

PLC810PG
LLC Soft Start
LLC Soft start is implemented by C_START (Figure 7). The LLC
starts at high frequency and ramps down until output regulation
is reached. Soft start is required as this allows the resonant
tank to begin to oscillate. It also prevents large LLC primary
currents during start-up that may trip the overcurrent threshold
on the ISL pin.
When the PLC810PG starts up, the FBL pin is internally pulled
up to VREF (3.25 V), and the LLC outputs are disabled. This
ensures that the soft start capacitor C_START discharged. The
FBL pin is then released falling to approximately 0.8 V; the
PLC810PG begins sensing the current into the FBL pin and the
LLC gate drive outputs begin switching. At start-up, the
optocoupler will have no current flowing (because the LLC
converter output is low) and the FBL pin current will be equal to
I . _FBLSTART As C_START charges, the current into the FBL pin
decreases, the LLC switching frequency decreases and the
LLC converter output rises. When regulation is reached, the
feedback loop closes and the optocoupler regulates the FBL
current. During normal operation, C_START remains charged and
does not have any current flow.
The start-up time constant is:
xSTART
=
C START
#
R3#
R3+
R4
R4
LLC Protection and Auto-Restart
The ISL pin senses LLC primary current via a sense resistor in
series with the bottom side of the transformer primary. An RC
low-pass filter is required, with recommended values of 1 kW
and 1 nF respectively. The ISL pin has 2 thresholds. The
higher threshold, V_ISL(F), will immediately shut off and protect the
LLC MOSFETs in the event of component failure. The lower
threshold, V_ISL(S), when exceeded for 8 consecutive cycles, also
shuts down the LLC protecting against output overcurrent.
Either fault mode will invoke an auto-restart sequence. When
either of these fault conditions occur, the FBL pin is pulled-up
internally to VREF, discharging the soft start capacitor. The
controller counts for 4096 clock cycles, then initiates a new
start-up (soft start) sequence. Typically 4096 cycles is sufficient
to completely discharge the soft start capacitor ensuring that
the LLC will re-start at frequency F_START.
Layout Considerations
PFC Powertrain Layout
PFC Layout
Boost
Choke
A
10 nF
500 V
Bulk Cap
PI-5277-111108
Figure 8. Power Elements in a Boost Converter Stage.
Figure 8 shows a typical PFC boost converter power stage
using a single bulk capacitor (some designs may use 2 because
of the ripple current requirement). With a single bulk capacitor,
the bulk capacitor should be closer to the PFC MOSFET than
the LLC MOSFETs. The PFC MOSFET, diode, and bulk
capacitor should be mounted close to each other, with short
leads connecting them. In addition, a 10 nF-47 nF high
frequency bypass capacitor is recommended to reduce EMI. It
should be connected close to the PFC MOSFET and diode, in
order to minimize loop area (“A” in the diagram). This loop area
sees the highest di/dt, and thus must be minimized. In some
cases, an optional damping resistor in series with the 10 nF
capacitor can reduce turn on Drain current ringing and
consequent EMI. The recommended value for this resistor is
between 0.2 W and 1 W.
LLC Powertrain Layout
Locating the Bulk Capacitor
If 2 parallel bulk capacitors are used to meet the ripple current
requirement, place 1 near the PFC MOSFET, and the second
near the LLC MOSFETs. If only one bulk capacitor is used, it is
recommended that a high voltage decoupling capacitor, (10 nF-
100 nF), is connected across the HVDC bus and primary return,
connected with short traces to the LLC MOSFETs. (See C40 in
schematic in Figure 4, and in PCB layout in Figure 9) The LLC
converter MOSFETs see high di/dt, and this high voltage
decoupling capacitor will reduce EMI.
High Voltage Pins
Three pins on the device have high voltage and high dv/dt
because they track the LLC MOSFET half-bridge output. These
are HB, VCCHB, and GATEH (pins 12, 13, and 14). These pins
must be isolated from the rest of the pins on the PLC810PG
(extra package isolation is also provided by omitting pins 11
and 15). Because these pins have high dv/dt, the traces and
components connected to them have to be kept away from low
voltage pins. Stray capacitance from these nodes to low
voltage, (high impedance) pins will cause noise-coupling and
erratic operation. Maintain 160 mil (4 mm) spacing between
these pins, and surrounding low voltage nodes. See highlighted
spacing in Figure 10.
Low Voltage Signal Pins
All pin decoupling capacitors must be mounted close to the IC
and with short traces to the pins. All decoupling capacitors
should be returned to the GND pin, with the exception of the
decoupling capacitors for VCCL, and VCCHB.
Several pins require external RC low-pass filters. There are the
ISP, ISL, FBP, and FBL pins. The capacitors and resistors
should be mounted close to the IC. This will prevent capacitive
coupling with high dv/dt nodes. The ISP pin is the input pin
with the smallest signal and the widest bandwidth. It not only
senses the average current in the PFC choke, it also senses
peak current in order to perform peak-to-peak current limiting
(to protect the PFC MOSFET). The current limiting function
requires wide bandwidth.
14
Rev. F 08/09
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