PLC810PG Datasheet, PDF(13/26 Page) Power Integrations, Inc. – Continuous Mode PFC & LLC Controller Continuous Mode PFC & LLC Controller

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PLC810PG Datasheet, PDF (13/26 Pages) Power Integrations, Inc. – Continuous Mode PFC & LLC Controller Continuous Mode PFC & LLC Controller

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PLC810PG

is a virtual short-circuit, the optocoupler is turned off and all

FBL pin current comes from R3.

VREF

CSTART

FBL

GND

CFBL

1 nF

COPTO

1 nF

U1B

PI-5276-121108

Figure 7. Typical LLC Feedback Network.

FBL pin

The FBL pin is the voltage regulation feedback pin. It sinks

current in normal operation. The greater the input current, the

higher the LLC switching frequency. The characteristic of

frequency versus the size of shunt resistor (connected to VREF)

is given in Figure 16. The FBL pin has a Thevenin equivalent

circuit of nominally 0.65 V and 3.3 kW. It should be noted that

the 1 nF decoupling Capacitor, CFBL (see Figure 7), in conjunction

with the 3.5 kW input resistance presented by the FBL pin,

form a pole in the LLC transfer function. This needs to be

considered as part of the LLC feedback loop. To insure loop

stability the 1 nF capacitor should not be increased.

A typical feedback network uses a TL431 and an optocoupler

for output regulation. The optocoupler regulates current

provided to the FBL pin. A resistor network between the

optocoupler and the FBL pin sets the minimum, maximum, and

start-up currents into the FBL pin.

In Figure 7 optocoupler U1B is connected to the FBL pin

through a resistor network comprised of resistors R1, R2, R3,

R4, and the Capacitor CSTART. CSTART is active only during soft

start and can be ignored during normal operation. Copto is a

filter capacitor that reduces noise from the long optocoupler

traces. The value (R3 + R4) sets the minimum FBL pin current

and therefore minimum LLC frequency, FMIN (when the

optocoupler is turned off). This occurs at the end of holdup

time, when the bulk capacitor has discharged down to 64%

(nominal) of the regulation set point.

The maximum FBL pin current (and therefore the maximum LLC

frequency that the feedback loop can command) is set by R2,

R3, and R4. Maximum frequency occurs when the optocoupler

is fully saturated, such as when the LLC output moves above

the set point during an output load dump. It should be noted

that if the maximum FBL pin current is greater than the FMAX

pin current, the LLC gate drivers turn both MOSFETs off.

The start-up current (and therefore the starting frequency), is

determined by the value of R3. Note that during start-up, CSTART

The procedure for selecting the resistor values is as follows.

Choose R1

This is the main load resistance in series with the optocoupler.

A value of 1.8 kW will yield good frequency response with an

acceptable maximum collector load current of approximately

2 mA. Note that the overall loop gain will be proportional to this

resistor value.

Choose FSTART (the initial frequency at start-up)

FSTART is typically chosen to be equal to or just less than FMAX.

Determine the resistance value that corresponds to the desired

FSTART from Figure 16. Set R3 to this value. R3 will typically

have a value close to that of the FMAX resistor.

The next step is to set FMIN. FMIN is the frequency that the LLC

needs in order to regulate at full load, FMIN is determined by the

sum of (R3 + R4). Look up the resistance value R for the

desired FMIN in Figure 16. Set R4 according to the equation

below.

R4= R - R3

Calculate the Value of R2

IFBL(MAX) is the current that flows into the FBL pin when the

optocoupler is saturated. This represents the maximum

frequency that the feedback loop can command via the FBL

pin. If this current is greater than the FMAX pin current (set by

the FMAX pin resistor), the LLC converter may be forced into

hysteretic burst-mode in order to regulate the output voltage at

zero or light load. If burst-mode is not desired, IFBL(max) must be

set less than the FMAX pin current. In this case, ensure that

there is sufficient dead-time given by the FMAX pin resistor. If

FMAX is less than the frequency needed for regulation at light

load, then burst mode operation will be required.

The relationship between IFBL (FBL pin current) and frequency is

given in Figure 17. The relationship between IFBL(max) and the

resistor values is given below (1):

I FBL (MAX)

VREF

- V I^ h FBL FBL(MAX

R3+ R4

+ VREF

VCESAT

VFBL

^ I h FBL(MAX)

(1)

VR2 (the voltage across R2) can be defined as:

VR 2 = VREF - VCESAT - VFBL ^ I h FBL(MAX) - VD

(2)

We can and then substitute this into (1) and rearrange:

R3+ R4

R 2 = VR2

I R 3 + I R4 - V + V ] I g FBL(MAX)

FBL(MAX)

REF

FBL FBL(MAX)

(3)

Where VFBL is a function of IFBL

VCESAT = VCE of optocoupler in saturation (typical 0.3 V)

VD = diode forward voltage drop

VREF = 3.25 V (nominal)

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Rev. F 08/09

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