PLC810PG Datasheet, PDF (12/26 Pages) Power Integrations, Inc. – Continuous Mode PFC & LLC Controller Continuous Mode PFC & LLC Controller

PLC810PG
of an operational transconductance amplifier (OTA). The output
of this OTA is connected to the VCOMP pin. The feedback loop
operates to keep the voltage on the FBP pin (and therefore the
PFC output voltage) to a fixed value, depending on the resistor
divider ratio. When the PFC output voltage is higher than the
set point, the transconductance amplifier will source current,
raising the voltage on the VCOMP pin. When the PFC output
voltage is lower than the set point, the transconductance
amplifier will sink current, lowering the voltage on VCOMP pin.
The gain of the stage is equal to the product of the OTA gain
(G_M), and the impedance of the network connected to the
VCOMP pin.
The PFC controller senses the voltage on the VCOMP pin. A
higher voltage tends to reduce the PFC MOSFET’s duty cycle,
while a lower voltage tends to increase it.
The VCOMP pin has a linear operating range of 0.5 V to 2.5 V,
and is scaled and multiplied by the average inductor current to
set D_OFF, the off-duty-cycle of the PFC gate signal. During
closed-loop steady state operation, the VCOMP voltage is a
function of the line voltage and the PFC load. A low voltage on
VCOMP signifies high power, while a high voltage corresponds
to low power.
The VCOMP pin is internally connected to an input of a multiplier
which is part of the PFC modulator. The linear range of this pin
is 0.5 V to 2.5 V. 0.5 V signifies maximum power, and 2.5 V
signifies minimum power.
The FBP pin has 3 start-up and shutdown voltage thresholds.
1. INH – Inhibits PFC start-up at low AC input voltage.
2. V_SD(H) – inhibits LLC start-up after PFC start-up. LLC start-up
is delayed until the PFC output voltage is close to its
regulation set point.
3. V_SD(L) – shuts down the LLC converter when the bulk cap has
discharged to a low voltage – typically at the end of holdup
time.
Before PFC start-up, the voltage on the bulk cap is approx-
imately equal to the peak of the input voltage, and INH acts as
an AC undervoltage lockout. After the PFC starts, the PFC
output voltage no longer tracks the input voltage and there is no
low AC voltage shutdown function.
For a typical design with a PFC voltage set point of 385 V, the
PFC is inhibited when bulk voltage <100 V (typical), which is
equivalent to VAC <71 V (typical). LLC start-up is inhibited until
the PFC output voltage reaches 368 V (typical). For the same
design, the LLC will shut down when the PFC output voltage
drops below 246 V (typical).
LLC Controller Section
The LLC converter is a variable frequency converter (an LLC
converter’s output power decreases as frequency increases).
The designer needs to set the minimum and maximum
frequencies of the PLC810PG to suit the power train.
FMAX Pin
The FMAX pin is connected via a programming resistor to the
VREF pin. This resistor programs the current into the FMAX
pin. This pin has a nominal Thevenin equivalent circuit of 0.65 V
and 1.5 kW. The programmed current into the FMAX pin
controls two parameters:
1. The LLC drive (GATEL and GATEH) dead-time. The smaller
the resistor value, the greater the current and the higher the
maximum frequency, see Figure 15.
2. The maximum LLC operating frequency. When the FBL pin
current increases above the FMAX pin current, the LLC
MOSFETs will be shut down. Switching will restart when the
FBL pin current drops below the FMAX pin current.
The dead-time should be longer than the actual voltage rise and
fall times of the LLC half-bridge center-point (longest times at
minimum load). If the programmed dead-time is shorter than
the actual rise and fall times, the MOSFETs will no longer
operate in the ZVS region, and losses will increase. Dead-times
somewhat longer than this required minimum have very little
impact on efficiency.
During long dead-times the body diodes of the LLC switching
MOSFETs will conduct current just before turn-on; the
additional conduction loss is very small compared to other
losses. The FMAX pin programming resistor sets both dead-
time and maximum frequency. Setting a longer dead-time than
that required at no-load is the recommended approach if a
lower maximum frequency is desired
.
If the required dead-time is very long, and the resulting F_MAX is
lower than that required for light load regulation (for the worst
case at maximum input voltage), then the solution is to limit F_MAX
and allow the LLC to enter burst-mode under light load
(maximum frequency) in order to keep the output in regulation.
Maximum input voltage occurs during a 100-0% load step
which causes the PFC output voltage to overshoot to VOV(H)
triggering the PFC output overvoltage protection circuit (which
is nominally 105% of the PFC nominal voltage set point). For a
typical design, an LLC converter requires an F_MAX of 1.5x ~ 2x
the nominal operating frequency (measured at full load and
nominal input voltage).
If burst-mode regulation is required for light load operation, the
FBL pin resistors must be chosen such that the maximum
current driven by the feedback loop into the FBL pin is greater
than the FMAX pin current (set by the FMAX pin resistor). When
the FBL pin current is greater than the FMAX pin current, the
LLC gate drivers turn off both MOSFETs. During line/load
conditions that require higher frequency than F_MAX to maintain
regulation, the LLC converter will go into hysteretic burst-mode
to maintain regulation.
When burst mode is used, care must be taken to ensure that
during startup, the peak primary currents do not trigger primary
over current (ISL pin). This is because switching frequency cannot
be higher than F_MAX (even during soft start) and the peak primary
currents with a low soft start frequency will therefore be higher.
12
Rev. F 08/09
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