PLC810PG Datasheet, PDF (15/26 Pages) Power Integrations, Inc. – Continuous Mode PFC & LLC Controller Continuous Mode PFC & LLC Controller

Figure 9. Location of LLC High Voltage Film Decoupling Capacitor, C40.
PLC810PG
Use an RC low-pass filter with time constant between 100 ns
and 200 ns, mounted near the device. The low-pass filter
capacitor should be returned to the GND pin. Mount the PFC
sense resistor close to the PFC MOSFET.
Run a dedicated trace from the GND pin to the junction of the
PFC MOSFET Source and the PFC sense resistor. There
should be no other connections on the trace from the GND pin
to the PFC/LLC power components.
Run a dedicated trace from the resistor of the RC low-pass filter
on the ISP pin to the PFC sense resistor. To avoid loop pick up
from di/dt noise that may effect signal integrity, this trace must
run alongside the trace from the GND pin to the PFC MOSFET
source.
Layout the PFC driver circuitry near the PFC MOSFET. Run the
trace connecting GATEP to the PFC driver circuitry adjacent to
the ISP trace to the sense resistor. It is preferable to have the
GND trace between the GATEP and ISP signal traces. This will
reduce potential noise coupling from the GATEP trace to the ISP
trace. See Figure 12.
FBL Pin Circuitry and Optocoupler
See Figure 13. The FBL pin circuitry should be mounted close
to the PLC810PG. The feedback optocoupler is typically
Isolation
Spacing
Figure 10. Isolation of High dv/dt Pins From Low Voltage Pins and Traces.
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PI-5283-111008
15
Rev. F 08/09