PLC810PG Datasheet, PDF (11/26 Pages) Power Integrations, Inc. – Continuous Mode PFC & LLC Controller Continuous Mode PFC & LLC Controller

PLC810PG
When the AC input voltage is low, Q7 and Q9 turn off, allowing
C22 to charge. Transistor Q6, R21, and VR3 sense the voltage
on C22. When C22 has charged sufficiently, Q6 turns on,
turning off the primary bias supply via Q5, shutting down the
PLC810 and thus the PFC and LLC stages.
Controller
Figure 4 shows the circuitry around the U13 main controller IC,
which provides control functions for the input PFC and output
LLC stages.
PFC Control
The PFC boost stage output voltage is fed back to the FBP pin
of the PLC810PG via resistors R39-41, R43, R46, and R50. A
10 nF capacitor (C25) filters noise. Capacitor C26, C28 and
R48 provide frequency compensation for the PFC. The PFC
current sense signal from resistors R6 and R8 is filtered by R45
and C24. The PFC drive signal is routed to the main switching
MOSFET via resistor R44, which damps any ringing in the PFC
drive signal caused by the trace length from the PLC810PG to
the PFC gate drive circuitry.
Bypassing/Ground Isolation
See “GND Pins” and “VCC Pins” under the section “Pin
Description”. Capacitors C29 and C32 provide decoupling for
the VCC pin. Capacitor C31 provides decoupling for the VCCL
pin. Resistor R37 is an optional resistor that provides additional
filtering for the VCC pin. This will help reject any noise picked
up by long VCC traces from the standby supply.
Capacitors C24, C25, C32, C29, C30, C31, C33, C34, C35
must be connected to the correct ground pins, and be
connected with short traces to the PLC810PG. See section
“Pin Description”.
Resistor R55 separates the GND and GNDL pins. Together
with ferrite bead L7, it provides high frequency isolation between
GND and GNDL pins. The GATEL output gate drive for the low-
side LLC MOSFET Q11 returns to GNDL through ferrite bead L7.
The GATEH output gate drive for the high-side LLC MOSFET
Q10 returns to HB through ferrite bead L6. This bead is
optional, but provides symmetry with L7.
LLC Control
Feedback from the LLC output sense/error amplifiers circuits is
provided by optocoupler U7. Resistor R54 is the optocoupler
load. Diode D16 allows the optocoupler to pull up on the LLC
feedback pin (FBL) only. See “LLC Controller section” for the
description of the functions performed by of R54, C36, R53,
R51, R49, and C27. The LLC current sense signal from resistor
R59 is filtered by R47 and C35. Capacitor C23, R42, and D8
provide the booststrap supply for the LLC high side MOSFET
driver. See “GND Pins” and “VCC Pins” under the section “Pin
Description”.
LLC Secondary Control Circuits
Figure 4 shows the secondary control schematic for the LLC
stage.
Voltage Feedback
The LLC converter 12 V and 24 V outputs are sensed, weighted,
and summed by resistors R64, R66, and R68. Resistor R62 is
the main gain-setting resistor. Resistor R63 and C45 form a
phase-lead compensator which extends the feedback loop’s
crossover frequency and increases the phase margin. Resistor
R67, C46 and C47, in conjunction with R68 set the low-
frequency compensation. Capacitor C48 is a “soft finish”
capacitor that reduces output overshoot at start up, by
conducting during the output rise time. It does not affect the
main feedback loop characteristics.
OVP
Zener diodes VR6-7 and D12, D13 sense any overvoltage
condition in the 12 V or 24 V outputs. An overvoltage signal
from either output is used to trigger a bipolar latch (Q14, Q15,
R70, R73), which turns on transistor Q13. This transistor is used
to deactivate the remote on-circuit which turns off the primary
bias, and hence the PLC810PG.
Power Supply Block Functions
and Key Design Details
PFC Control Section
The PFC controller uses continuous conduction mode, with an
off-duty-cycle control algorithm. This approach removes the
requirement for input AC voltage sensing. The off-time is
proportional to the product of the average inductor current
(averaged over several switching cycles), and the error amp
output. This automatically shapes the average input current, to
the same shape as the input AC voltage.
The PLC810PG PFC circuit is frequency and phase locked to
the LLC circuit. PLC810PG employs collision avoidance
technology, where the PFC edges straddle those of the LLC so
that simultaneous edge transitions in both the PFC and LLC
sections are prevented. This reduces interference between
PFC and the LLC circuits.
The PFC section has 2 input pins: a current sense input (ISP
pin), and a voltage feedback input (FBP pin). There are 2 output
pins. A VCOMP pin for placing the feedback compensation
components, and a MOSFET gate signal output designed to
work with an external MOSFET driver.
Inductor current is sensed via the ISP pin which monitors the
negative voltage developed across the PFC current sense
resistor. This resistor is connected to the PFC MOSFET Source
pin. The current is averaged over several switching cycles and
is used for the PFC control algorithm. This pin also implements
a cycle-by-cycle current limit to protect the PFC MOSFET in the
event of a short-circuit. The RC filter with 100-200 ns time
constant attenuates high frequency switching noise, but must
be fast enough to detect a saturating PFC inductor in order to
protect the PFC MOSFET.
PFC output voltage is sensed by the FBP pin via a resistor
voltage divider network. The FBP pin is connected to the input
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Rev. F 08/09