PLC810PG Datasheet, PDF (16/26 Pages) Power Integrations, Inc. – Continuous Mode PFC & LLC Controller Continuous Mode PFC & LLC Controller

PLC810PG
HiperPLC
FBL pin parts
near HiperPLC
Route opto traces side-by-side
all the way to HiperPLC
Gate resistors
next to LLC
MOSFETs
HB and GATEH
traces side-by-side _{GNDL and GATEL}
traces side-by-side
R15
PI-5281-111308
Figure 11. Gate Drive and Feedback PCB Layout Recommendations.
mounted far away from the IC. The 2 traces from the optocoupler
(emitter and collector), should be run side by side to the FBL
circuitry. This minimizes loop area and limits stray di/dt
(inductive) noise coupling.
GATEL and GNDL
See Figure 11. The lines from GATEL pin, and the GNDL pins,
which go to the LLC low side MOSFET Gate and Source
respectively, should run side by side. The GNDL pin should be
connected to the LLC low MOSFET Source pin via a ferrite
bead. The gate resistor (R28) should also be mounted close to
the MOSFET.
HB and GATEH
Refer to Figure 11. The HB and GATEH lines should run side by
side from the LLC high side MOSFET to the PLC810PG. The
gate resistor (R26) should be mounted close to the MOSFET.
Recommended PFC Gate Drive Circuit
Figure 13 shows the recommended PFC MOSFET gate drive
circuit. This circuit needs to be placed close to the PFC
MOSFET. The gate turn-off current is limited by R33, while gate
turn-on current is limited by the sum of the values of R33 and
R4. Resistor R4 also prevents high shoot-through currents
flowing through both BJTs during switching edges. The resistor
R4 is placed in series with the collector of Q8 instead of the
emitter, as this will prevent negative Vbe voltage in Q8 which
can lead to break down of the junction. Resistors R3 and R4
have a strong effect on PFC efficiency, and EMI. The local 1 mF
bypass capacitor, C28, needs to be mounted close to the BJTs
(Q8 and Q9). Resistor R107 is for keeping the MOSFET off
when the PLC810PG is unpowered.
16
Rev. F 08/09
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