74F841 Datasheet, PDF (8/18 Pages) NXP Semiconductors – Bus interface latches

Philips Semiconductors
Bus interface latches
Product specification
74F841/74F842/74F843/
74F845/74F846
LOGIC DIAGRAM for 74F845
PRE ¹⁴
D0
D1
D2
D3
D4
D5
D6
D7
3
4
5
6
7
8
9
10
MR ¹¹
LE ¹³
OE0 ¹
OE1 ²
23
OE2
V_CC = Pin 24
GND = Pin 12
DP
LQ
C
DP
LQ
C
DP
LQ
C
DP
LQ
C
DP
LQ
C
DP
LQ
C
DP
LQ
C
DP
LQ
C
22
Q0
21
Q1
20
Q2
19
Q3
18
Q4
17
Q5
16
Q6
15
Q7
SF01301
LOGIC DIAGRAM for 74F846
PRE ¹⁴
D0
D1
D2
D3
D4
D5
D6
D7
3
4
5
6
7
8
9
10
MR ¹¹
LE ¹³
OE0 ¹
OE1 ²
23
OE2
V_CC = Pin 24
GND = Pin 12
DP
LQ
C
DP
LQ
C
DP
LQ
C
DP
LQ
C
DP
LQ
C
DP
LQ
C
DP
LQ
C
DP
LQ
C
22
Q0
21
Q1
20
Q2
19
Q3
18
Q4
17
Q5
16
Q6
15
Q7
SF01302
FUNCTION TABLE for 74F845 and 74F846
INPUTS
OE
PRE
MR
LE
Dn
L
L
X
X
X
L
H
L
X
X
L
H
H
H
L
L
H
H
H
H
L
H
H
↓
l
L
H
H
↓
h
H
X
X
X
X
L
H
H
L
X
H=
L=
h=
l=
↓=
X=
NC=
Z=
High voltage level
Low voltage level
High state one setup time before the High-to-Low LE transition
Low state one setup time before the High-to-Low LE transition
High-to-Low transition
Don’t care
No change
High impedance “off” state
OUTPUTS
74F845
74F846
Qn
Qn
H
H
L
L
L
H
H
L
L
H
H
L
Z
Z
NC
NC
OPERATING MODE
Preset
Clear
Transparent
Latched
High Impedance
Hold
1999 Jun 23
8