74F841 Datasheet, PDF (2/18 Pages) NXP Semiconductors – Bus interface latches

Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/
74F845/74F846
74F841/74F842 10-bit bus interface latches, non-inverting/inverting (3-State)
74F843 9-bit bus interface latch, non-inverting (3-State)
74F845/74F846 8-bit bus interface latches, non-inverting/inverting (3-State)
FEATURES
• High speed parallel latches
• Extra data width for wide address/data paths or buses carrying
parity
• High impedance NPN base input structure minimizes bus loading
• IIL is 20µA vs 1000A for AM29841 series
• Buffered control inputs to reduce AC effects
• Ideal where high speed, light loading, or increased fan-in are
required as with MOS microprocessors
• Positive and negative over-shoots are clamped to ground
• 3-State outputs glitch free during power-up and power-down
• 48mA sink current
• Slim dual in-line 300 mil package
• Broadside pinout
• Pin-for-pin and function compatible with AMD AM29841-846
series
TYPE
74F841, 74F842
74F843, 74F845
74F846
TYPICAL
PROPAGATION
DELAY
5.5ns
5.5ns
6.2ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
60mA
75mA
60mA
DESCRIPTION
The 74F841–74F846 bus interface latch series are designed to
provide extra data width for wider address/data paths of buses
carrying parity.
The 74F841–74F846 series are funcitonally an pin compatible to the
AMD AM29841–AM29846 series.
The 74F841 consists of ten D-type latches with 3-State outputs. The
flip-flops appear transparent to the data when Latch Enable (LE) is
High. This allows asynchronous operation, as the output transition
follows the data in transition. On the LE High-to-Low transition, the
data that meets the setup and hold time is latched.
Data appears on the bus when the Output Enable (OE) is Low.
When OE is High the output is in the High-impedance state.
The 74F842 is the inverted output version of the 74F841.
The 74F843 consists of nine D-type latches with 3-State outputs. In
addition to the LE and OE pins, the 74F843 has a Master Reset
(MR) pin and Preset (PRE) pin. These pins are ideal for parity bus
interfacing in high performance systems. When MR is Low, the
outputs are Low if OE is Low. When MR is High, data can be
entered into the latch. When PRE is Low, the outputs are High, if OE
is Low, PRE overrides MR.
The 74F845 consists of eight D-type latches with 3-State outputs. In
addition to the LE, OE, MR and PRE pins, the 74F845 has two
addtitional OE pins making a total of three Output Enables (OE0,
OE1, OE2) pins.
The multiple Ouptut Enables (OE0, OE1, OE2) allow multi-user
control of the interface, e.g., CS, DMA, and RD/WR.
The 74F846 is the inverted output version of the 74F845.
ORDERING INFORMATION
PACKAGES
24-pin plastic Slim DIP (300 mil)
24-pin plastic SOL
COMMERCIAL RANGE
V_CC = 5V±10%; T_amb = 0°C to +70°C
N74F841N, N74F842N, N74F843N, N74F845N, N74F846N
N74F841D, N74F842D, N74F843D, N74F845D, N74F846D
PACKAGE DRAWING
NUMBER
SOT222-1
SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
Dn
Data inputs
1.0/0.033
LE
Latch Enable input
1.0/0.033
OE, OEn
Output Enable input (active Low)
1.0/0.033
MR
Master Reset input (active Low)
1.0/0.033
PRE
Preset input (active Low)
1.0/0.033
Qn
Data outputs
1200/80
Qn
Data outputs
1200/80
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOAD VALUE
HIGH/LOW
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
24mA/48mA
24mA/48mA
1999 Jun 23
2
853–1208 21851