74F841 Datasheet, PDF (7/18 Pages) NXP Semiconductors – Bus interface latches

Philips Semiconductors
Bus interface latches
Product specification
74F841/74F842/74F843/
74F845/74F846
LOGIC DIAGRAM for 74F843
PRE ¹⁴
D0
D1
2
3
DP
DP
MR ¹¹
LE ¹³
LQ
C
LQ
C
D2
4
DP
LQ
C
D3
5
DP
LQ
C
D4
6
DP
LQ
C
D5
7
DP
LQ
C
D6
8
DP
LQ
C
D7
9
DP
LQ
C
D8
10
DP
LQ
C
OE ¹
V_CC = Pin 24
GND = Pin 12
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
FUNCTION TABLE for 74F843
INPUTS
OE
PRE
MR
LE
Dn
L
L
X
X
X
L
H
L
X
X
L
H
H
H
L
L
H
H
H
H
L
H
H
↓
l
L
H
H
↓
h
H
X
X
X
X
L
H
H
L
X
H=
L=
h=
l=
↓=
X=
NC=
Z=
High voltage level
Low voltage level
High state one setup time before the High-to-Low LE transition
Low state one setup time before the High-to-Low LE transition
High-to-Low transition
Don’t care
No change
High impedance “off” state
OUTPUTS
74F843
Qn
H
L
L
H
L
H
Z
NC
18
Q5
17
Q6
16
Q7
15
Q8
SF01299
OPERATING MODE
Preset
Clear
Transparent
Latched
High Impedance
Hold
1999 Jun 23
7