74F841 Datasheet, PDF (6/18 Pages) NXP Semiconductors – Bus interface latches

Philips Semiconductors
Bus interface latches
Product specification
74F841/74F842/74F843/
74F845/74F846
LOGIC DIAGRAM for 74F841
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
2
3
4
5
6
7
8
9
10
11
D
LQ
D
LQ
D
LQ
D
LQ
D
LQ
D
LQ
D
LQ
C
D
LQ
D
LQ
D
LQ
LE ¹³
OE ¹
V_CC = Pin 24
GND = Pin 12
23
Q0
22
Q1
LOGIC DIAGRAM for 74F842
D0
D1
D2
2
3
4
21
Q2
D3
5
20
Q3
D4
6
19
Q4
D5
7
18
Q5
D6
8
17
Q6
D7
9
16
Q7
15
Q8
14
Q9
SF01297
D8
10
D9
11
D
LQ
D
LQ
D
LQ
D
LQ
D
LQ
D
LQ
D
LQ
C
D
LQ
D
LQ
D
LQ
LE ¹³
OE ¹
V_CC = Pin 24
GND = Pin 12
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
FUNCTION TABLE for 74F841 and 74F842
INPUTS
OUTPUTS
74F841
74F842
OE
LE
Dn
Qn
Qn
L
H
L
L
H
L
H
H
H
L
L
↓
l
L
H
L
↓
h
H
L
H
X
X
Z
Z
L
L
X
NC
NC
H=
L=
h=
l=
↓=
X=
NC=
Z=
High voltage level
Low voltage level
High state one setup time before the High-to-Low LE transition
Low state one setup time before the High-to-Low LE transition
High-to-Low transition
Don’t care
No change
High impedance “off” state
18
Q5
17
Q6
16
Q7
15
Q8
14
Q9
SF01298
OPERATING MODE
Transparent
Latched
High Impedance
Hold
1999 Jun 23
6