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| 74F841 Datasheet, PDF (15/18 Pages) NXP Semiconductors – Bus interface latches | |||
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Philips Semiconductors
Bus interface latches
Product specification
74F841/74F842/74F843/
74F845/74F846
TEST CIRCUIT AND WAVEFORMS
VCC
VIN
PULSE
GENERATOR
VOUT
RL
D.U.T.
RT
CL RL
Test Circuit for 3-State Outputs
SWITCH POSITION
TEST
tPLZ
tPZL
All other
SWITCH
closed
closed
open
7.0V
90%
NEGATIVE
PULSE
POSITIVE
PULSE
10%
tw
VM
10%
tTHL (tf )
VM
10%
tTLH (tr )
tTLH (tr )
90%
VM
tw
tTHL (tf )
90%
VM
Input Pulse Definition
90%
AMP (V)
0V
AMP (V)
10%
0V
DEFINITIONS:
RL = Load resistor;
see AC electrical characteristics for value.
CL = Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
INPUT PULSE REQUIREMENTS
family
amplitude VM rep. rate
tw
tTLH
74F
3.0V 1.5V 1MHz 500ns 2.5ns
tTHL
2.5ns
SF00777
1999 Jun 23
15
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