SAA7380 Datasheet, PDF (6/60 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM ELM

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (ELM)
Preliminary specification
SAA7380
SYMBOL
PIN
DGND4
41
CS1/HEN
42
HWR
43
HRD
44
DMACK
45
IORDY/WAIT/HFBLB 46
SCRST/STEN
47
DMARQ/DTEN
48
IRQ/EOP/HFBC
49
V_DDD2
50
HD0
51
HD1
52
HD2
53
HD3
54
HD4
55
HD5
56
HD6
57
HD7
58
DGND5
59
HD8
60
HD9
61
HD10
62
HD11
63
HD12
64
HD13
65
HD14
66
HD15
67
DGND6
68
DA0/CMD
69
DA1
70
DA2/EJECT
71
CS2/SELRQ
72
IOCS16
73
V_DDD2
74
RA0
75
RA1
76
RA2
77
I/O
DESCRIPTION
− digital ground 4
I host interface enable input (active LOW)
I host interface write enable input (active LOW)
I host interface read enable input (active LOW)
I DMA acknowledge input
O host interface wait output (active LOW); 3-state control
O host interface status enable output ATAPI sub-CPU reset signal
(active LOW)
O ATAPI DMA request host interface data enable output (active LOW);
3-state control
O host interface end of process flag output ATAPI host interrupt request
(active LOW); 3-state control
− digital supply voltage 2 (5 V)
I/O host interface data bus input/output line 0
I/O host interface database input/output line 1
I/O host interface database input/output line 2
I/O host interface data bus input/output line 3
I/O host interface data bus input/output line 4
I/O host interface data bus input/output line 5
I/O host interface data bus input/output line 6
I/O host interface data bus input/output line 7
− digital ground 5
I/O host interface data bus input/output line 8
I/O host interface data bus input/output line 9
I/O host interface data bus input/output line 10
I/O host interface data bus input/output line 11
I/O host interface data bus input/output line 12
I/O host interface data bus input/output line 13
I/O host interface data bus input/output line 14
I/O host interface data bus input/output line 15
− digital ground 6
I host interface data input (active LOW)/command select input host interface
address line 0
I ATAPI address line input 1
I ATAPI address line input 2
I ATAPI chip select input 2
O ATAPI 16-bit data select output
− digital supply voltage 2 (5 V)
O buffer RAM address bus output line 0
O buffer RAM address bus output line 1
O buffer RAM address bus output line 2
1996 Apr 25
6