SAA7380 Datasheet, PDF (29/60 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM ELM

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (ELM)
Preliminary specification
SAA7380
Table 30 Description of registers
REGISTER
DESCRIPTION
DATA
This is a 16-bit register and is used for transferring data to and from the host. This should only be
performed after the Sub-CPU has initiated the data transfer.
AFEAT
This is the ATAPI Features register.
AERR
This is the ATAPI Error register.
AINTR
This is the ATAPI Interrupt Reason register.
ASAMT
This is the ATAPI Sector Count register.
DBCL and These are the ATAPI Byte Count registers.
DBCH
ADRSEL
This is the ATAPI Drive Select register (see Table 31). Bit 4 of this register is the DRV bit. When this bit
is the same as the RDRV bit in the DTCTR register then SAA7380 will be the selected ATAPI drive and
will respond to commands and produce interrupts. The host Interrupt pin will also be enabled when
SAA7380 is the selected drive.
ACMD
This is the ATAPI Command register. A CMDI interrupt is generated when the host writes to this
register while SAA7380 is the selected drive (the DRV bit in ADRSEL is equal to the RDRV bit in
DTCTR) and when the host writes the execute drive diagnostic command (90H) to this register. If a
host interrupt is asserted then it will be cleared by writing to this register.
ASTAT
This is the ATAPI Status register. Bit 7 is the BSY bit and this will be set whenever the host writes to
the ACMD register and SAA7380 is the selected drive, when the host writes the execute drive
diagnostic command (90H) to the ACMD register, when the host writes to the ADCTR register and sets
the SRST bit and when there is a hardware reset. If a host interrupt is asserted then it will be cleared by
writing to this register.
ALT STATUS This is the ATAPI Alternative Status register. This is identical to the ASTAT register except reading this
register does not negate the host interrupt.
ADCTR
This is the ATAPI Device Control register (see Table 32)
ADRADR This is the ATAPI Drive Address register. Bit 7 of this register is high impedance.
Table 31 ADRSEL register bits
BIT 7
BIT 6
BIT 5
1
1
1
BIT 4
DRV
BIT 3
−
BIT 2
−
BIT 1
−
BIT 0
−
Table 32 ADCTR register bits
BIT 7
BIT 6
BIT 5
reserved
BIT 4
BIT 3
1
BIT 2
SRST
BIT 1
nIEN
BIT 0
0
Setting the SRST bit HIGH causes a SRSTI interrupt and the BSY bit to be set.
Bit nIEN is used to enable or disable the host interrupt. When nIEN is logic 0 and the drive is selected then the host
interrupt pin will be enabled. If nIEN is logic 1 or the drive is not selected then the host interrupt pin will be in a
high-impedance state.
1996 Apr 25
29