SAA7380 Datasheet, PDF (22/60 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM ELM

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (ELM)
Preliminary specification
SAA7380
7.7.21 MEMS
This register is used to specify the configuration of the external buffer memory.
Table 19 MEMS register bits
BIT
7
6
5
NAME
DESCRIPTION
PRIORITY Host priority access. These bits specify the external memory accesses priority.
PRIORITY
4
−
−
3
RFRSH
DRAM refresh rate. Setting this bit specifies a DRAM refresh rate of clock
frequency/400. Clearing this bit specifies a rate of clock frequency/200. WIth a 33 MHz
clock this bit should be set, while with a 16 MHz clock the bit should be clear.
2
WIDTH
DRAM width select. This bit should be set if the external DRAM has a nibble wide data
bus. If the data bus is byte wide then this bit should be clear.
1
STATIC
SRAM/DRAM select. If the external buffer memory is DRAM then this bit should be
cleared. If the memory is SRAM this bit should be set.
0
CACHE
CACHE memory select. If the internal cache is available then this bit should be clear.
Setting this bit to logic 1 indicates that there is no internal cache memory.
Table 20 Host priority access
PRIORITY BITS
BIT 6
BIT 5
ACCESS
0
0
only one host access has highest priority
0
1
two successive host accesses have highest priority
1
0
three successive host accesses have highest priority
1
1
four successive host accesses have highest priority
7.7.22 ITRG
In the ATAPI mode writing to this register generates a host
interrupt. This interrupt is cleared when the host reads the
ATAPI status register or writes to the ATAPI command
register.
In the Sanyo and Oak compatibility modes writing to this
register has no effect.
7.7.23 ASTAT
This write only register is only available in the ATAPI
mode; it is the ATAPI status register and is used to transfer
status information to the ATAPI host.
Bit 7 of this register is the BSY bit and this is set by the
SAA7380 whenever;
• SAA7380 is the selected drive and the host writes to the
command register (ACMD)
• The host writes the execute drive diagnostic command
(90h) to the command register
• The host writes to the device control register (ADCTR)
and sets the SRST bit
• There is a hardware reset.
On reset this register is set to (80H).
1996 Apr 25
22