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SAA7380 Datasheet, PDF (42/60 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM ELM
◁
Philips Semiconductors
Error correction and host interface IC for
CD-ROM (ELM)
Preliminary specification
SAA7380
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP.
t7
HWR/HRD inactive
t8
HWR data set-up
t9
HWR data hold
t10
HRD data access
t11
HRD data to 3-state
t12
cycle time
33 MHz clock
16 MHz clock
60
−
145
−
50
−
20
−
−
−
5
−
3CLK −
8-BIT DMA DATA TRANSFER; see Fig.23
t0
DMARQ to DMACK
t1
HWR/HRD to DMARQ inactive
t2
DMACK set-up
t3
DMACK hold
t4
HWR/HRD active
33 MHz clock
16 MHz clock
t5
HWR/HRD inactive
33 MHz clock
16 MHz clock
0
−
−
−
30
−
0
−
50
−
75
−
60
−
145
−
t6
HWR data set-up
t7
HWR data hold
t8
HRD data access
t9
HRD data to 3-state
50
−
20
−
−
−
−
−
PSEUDO 16-BIT DMA READ TRANSFER; see Fig.24; note 4
t0
HRD to DMARQ inactive
t1
DMARQ to DMACK
t2
HRD inactive to DMACK inactive
t3
HRD active
33 MHz clock
16 MHz clock
t4
HFBC to data valid
t5
data 3-state to HFBC inactive
t6
HRD data access
t7
HRD data to 3-state
t8
HFBC active
t9
data valid to HFBLB
t10
HFBLB to HFBC inactive
−
−
0
−
0
−
50
−
65
−
−
−
CLK
−
−
−
−
−
−
−
2CLK −
2CLK −
Notes
1. All timings are for single-speed, they should be divided by the speed up to eight times speed.
2. T represents half a clock period.
3. The timings for this mode can only be met with a 33 MHz clock.
4. CLK = 1 clock period.
MAX.
−
−
−
−
80
60
−
UNIT
ns
ns
ns
ns
ns
ns
ns
−
ns
80
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
80
ns
60
ns
80
ns
−
ns
−
ns
−
ns
−
ns
CLK ns
−
ns
80
ns
60
ns
5CLK ns
−
ns
−
ns
1996 Apr 25
42
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