SAA7380 Datasheet, PDF (27/60 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM ELM

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (ELM)
Preliminary specification
SAA7380
7.9.1.3 Data Transfer
The other registers are used for data transfers. These can only occur when the sub-CPU has enabled a data transfer.
This will be indicated to the host by the DTEN pin being LOW.
7.9.2 OAK COMPATIBILITY MODE
Table 26 Oak compatibility mode
DMACK HEN⁽¹⁾ DA1⁽¹⁾ DA0⁽¹⁾
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
1
X
X
0
X
X
X
0
X
X
X
Note
1. Where X = don’t care.
HRD⁽¹⁾
1
0
1
0
1
0
1
X
1
0
HWR⁽¹⁾
0
1
0
1
0
1
0
X
0
1
DATA TRANSFER
SELECTED⁽¹⁾
NO
NO
YES
YES
X
X
X
X
X
X
OPERATION
write COMIN
read SBOUT
write data
read data
RESET sub-CPU
read TSTAT
write HCON
none
write DMA data
read DMA data
Data transfer is selected when the transfer type is non-DMA, the sub-CPU has started a data transfer and the DTS bit in
the HCON register has not been asserted.
DMA transfer is selected using the HCON register.
The COMIN and SBOUT registers are similar to the same registers in the Sanyo compatibility mode.
7.9.2.1 RESET Sub-CPU
Writing to this register causes the SCRST pin to go LOW for several clock periods. The SAA7380 registers are not
affected.
7.9.2.2 TSTAT
Table 27 TSTAT register bits
BIT 7
1
BIT 6
1
BIT 5
EJECT
BIT 4
WAIT
BIT 3
EOP
BIT 2
STEN
BIT 1
DTEN
BIT 0
DRQ
This is the host Transfer Status Register. The EJECT bit reflects the state of the EJECT pin. Bits EOP, STEN and DTEN
have the same operation as the equivalent pins in the Sanyo compatibility mode. Bit WAIT is the same as the Sanyo
mode WAIT pin when non-DMA transfer is selected otherwise it is logic 1. Bit DRQ is the same as the Sanyo mode WAIT
pin when DMA transfer is selected otherwise it is logic 0.
1996 Apr 25
27