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SAA7380 Datasheet, PDF (38/60 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM ELM
◁
Philips Semiconductors
Error correction and host interface IC for
CD-ROM (ELM)
Preliminary specification
SAA7380
SYMBOL
PARAMETER
Sub-CPU timing; see Fig.13
t0
syn to first SCL
t1
SCL cycle time
t2
time between bytes
t3
data set-up
t4
data hold
t5
data access
ATAPI host interface timing; see Fig.14
PIO 8 AND 16-BIT TRANSFER
t0
cycle time
t1
address to HWR/HRD set-up
t2
HWR/HRD active
t2i
HWR/HRD inactive
t3
HWR data set-up
t4
HWR data hold
t5
HRD data set-up
t6
HRD data 3-state
t7
address to IOCS16
t8
address to IOCS16 negate
t9
HWR/HRD to address hold
t10
IORDY set-up
t11
IORDY width
t12
read data valid to IORDY active
SINGLE-WORD DMA TRANSFER; see Fig.15
t0
cycle time
t1
DMACK to DMARQ
t2
DMACK to HWR/HRD
t3
HWR/HRD active
t4
HWR/HRD to DMACK hold
t5
HWR data set-up
t6
HWR data hold
t7
HRD data access
t8
HRD data hold
CONDITIONS
MIN. TYP. MAX. UNIT
250
−
500
−
250
−
150
−
0
−
−
−
−
ns
−
ns
−
ns
−
ns
−
ns
150
ns
33 MHz clock
150
−
16 MHz clock
240
−
30
−
33 MHz clock
80
−
16 MHz clock
100
−
33 MHz clock
70
−
16 MHz clock
140
−
30
−
10
−
50
−
−
−
only for 16-bit data register −
−
only for 16-bit data register −
−
10
−
−
−
only if IORDY negated
−
−
only if IORDY negated
0
−
33 MHz clock
16 MHz clock
33 MHz clock
16 MHz clock
240
−
480
−
−
−
0
−
120
−
240
−
0
−
35
−
20
−
−
−
5
−
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
30
ns
30
ns
30
ns
−
ns
35
ns
1250 ns
−
ns
−
ns
−
ns
80
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
60
ns
−
ns
1996 Apr 25
38
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