SAA7380 Datasheet, PDF (21/60 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM ELM

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (ELM)
Preliminary specification
SAA7380
Table 17 HSEL bits
HSEL CONTENT
BIT 2
0
0
0
0
BIT 1
0
0
1
1
others
BIT 0
0
1
0
1
SELECTED HOST
INTERFACE
DESCRIPTION
Sanyo
ATAPI
Oak
unknown host
reserved
Sanyo compatible mode
ATAPI Mode
Oak compatible mode
all host bus pins 3-state, default after h/w reset
for future enhancements
7.7.19 SUB_L, SUB_H
This 10-bit register specifies the memory address of the subcode data block. This address will always be in the first
1 kbyte of memory.
7.7.20 INCNF
This register is used to specify the configuration of the input data path.
Table 18 INCNF register bits
BIT
7
6
5
4
3
2
1
0
NAME
IISmode
div1⁽¹⁾
div0⁽¹⁾
QWmode
QWon
QWcook
RAMtest
−
DESCRIPTION
I²S-bus mode = 0; EIAJ serial interface mode = 1.
If div1 and div0 = logic 0 then no oversampling (normal CDROM modes); If div1 = logic 0
and div0 = logic 1 then 2 times oversampling; If div1 = logic 1 and div0 = logic 0 then
4 times oversampling.
If div1 and div0 = logic 0 then no oversampling (normal CDROM modes); If div0 = logic 1
and div1 = logic 0 then 2 times oversampling; If div1 = logic 0 and div1 = logic 0 then
4 times oversampling.
Selection of Q-to-W input format. Logic 0 = V4 mode; logic 1 = EIAJ mode.
Q-to-W interface enable. Logic 0 = off; logic 1 = on.
Q-to-W interface cooking enable. Logic 0 = cooked mode; logic 1 = RAW mode.
External RAM test mode. Logic 0 = normal operation; logic 1 = RAM test mode.
−
Note
1. For subcode Q-to-W recovery, the BCK clock is used as a timing reference. It is possible to recover the Q-to-W
subcode using the SAA7380, while at the same time the serial interface is programmed in oversampling mode for a
DAC. Under such circumstances, it is necessary to tell the SAA7380 the oversampling factor.
1996 Apr 25
21