SAA7380 Datasheet, PDF (5/60 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM ELM

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (ELM)
Preliminary specification
SAA7380
6 PINNING
SYMBOL
DGND1
RA6
RA7
RA8
RA9
RA10
RA11
RA12
RA13
RA14
RA15/RAS
RA16/CAS
RWE
DGND2
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
TEST2
DGND3
TEST1
CROUT
CRIN
SFSY
RCK
SUB
BCK
V_DDD1
WS
DATA
C2PO
SDA
SCL
INT
RESET
SYN
1996 Apr 25
PIN I/O
DESCRIPTION
1
− digital ground 1
2
O buffer RAM address bus output line 6
3
O buffer RAM address bus output line 7
4
O buffer RAM address bus output line 8
5
O buffer RAM address bus output line 9
6
O buffer RAM address bus output line 10
7
O buffer RAM address bus output line 11 (SRAM) only
8
O buffer RAM address bus output line 12 (SRAM) only
9
O buffer RAM address bus output line 13 (SRAM) only
10
O buffer RAM address bus output line 14 (SRAM) only
11
O buffer RAM address bus output line 15 (SRAM) or RAS (DRAM)
12
O buffer RAM address bus output line 16 (SRAM) or CAS (DRAM)
13
O buffer RAM write enable output
14
− digital ground 2
15 I/O buffer RAM data bus bidirectional line 0
16 I/O buffer RAM data bus bidirectional line 1
17 I/O buffer RAM data bus bidirectional line 2
18 I/O buffer RAM data bus bidirectional line 3
19 I/O buffer RAM data bus bidirectional line 4
20 I/O buffer RAM data bus bidirectional line 5
21 I/O buffer RAM data bus bidirectional line 6
22 I/O buffer RAM data bus bidirectional line 7
23
I test input 2
24
− digital ground 3
25
I test input 1
26
O clock oscillator output
27
I clock oscillator input
28
I serial subcode input frame sync input
29
O serial subcode clock output (active LOW)
30
I serial input for Q-to-W subcode input
31
I serial interface bit clock input
32
− digital supply voltage 1 (3.3 V)
33
I serial interface word clock input
34
I serial data input
35
I serial interface flag input
36 I/O sub-CPU serial data input/output
37
I sub-CPU serial clock input
38
O sub-CPU open-collector interrupt output
39
I power-on reset input (active LOW)
40
I sync signal input from sub-CPU
5