SAA7182A Datasheet, PDF (6/45 Pages) NXP Semiconductors – Digital Video Encoder EURO-DENC2

Philips Semiconductors
Digital Video Encoder (EURO-DENC2)
Preliminary specification
SAA7182A; SAA7183A
PINNING
SYMBOL
RESET
n.c.
V_SSD1
SA
V_DDD1
OVL2
OVL1
OVL0
KEY
DP0
DP1
DP2
DP3
V_DDD2
V_SSD2
DP4
DP5
DP6
DP7
TTXRQ
TTX
V_DDD3
n.c.
V_SSD3
MP7
MP6
MP5
MP4
V_DDD4
V_SSD4
MP3
MP2
MP1
MP0
RCV1
RCV2
PIN
PLCC84 QFP80
1
73
2
−
3
6
4
75
5
13
6
77
7
78
8
79
9
80
10
1
11
2
12
3
13
4
14
5
15
14
16
7
17
8
18
9
19
10
20
11
21
12
22
28
23
−
24
20
25
15
26
16
27
17
28
18
29
19
30
29
31
21
32
22
33
23
34
24
35
25
36
26
DESCRIPTION
Reset input, active LOW. After reset is applied, all digital I/Os are in input mode.
The I²C-bus receiver waits for the START condition.
not connected
digital ground 1
The I²C-bus slave address select input pin. LOW: slave address = 88H,
HIGH = 8CH.
digital supply voltage 1 (3.3 V)
3-bit overlay data input. This is the index for the internal look-up table.
Key input for OVL. When HIGH it selects OVL input.
Lower 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode
is used.
digital supply voltage 2 (5 V)
digital ground 2
Upper 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode
is used.
Teletext request output, indicating when bit stream is valid.
Teletext bit stream input.
digital supply voltage 3 (3.3 V)
not connected
digital ground 1
Upper 4 bits of MPEG port. It is an input for “CCIR 656” style multiplexed Cb, Y, Cr
data, or for Y data only, if 16 line input mode is used.
digital supply voltage 4 (5 V)
digital ground 4
Lower 4 bits of MPEG port. It is an input for “CCIR 656” style multiplexed Cb, Y, Cr
data, or for Y data only, if 16 line input mode is used.
Raster Control 1 for video port. This pin receives/provides a VS/FS/FSEQ signal.
Raster Control 2 for video port. This pin provides an HS pulse of programmable
length or receives an HS pulse.
1996 Oct 02
6