SAA7182A Datasheet, PDF (34/45 Pages) NXP Semiconductors – Digital Video Encoder EURO-DENC2

Philips Semiconductors
Digital Video Encoder (EURO-DENC2)
Preliminary specification
SAA7182A; SAA7183A
CHARACTERISTICS
V_DDD(3) = 3.0 to 3.6 V; V_DDD(5) = 4.75 to 5.25 V; T_amb = 0 to +70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Supply
V_DDA(3)
V_DDD(3)
V_DDD(5)
I_DDA
I_DDD(3)
I_DDD(5)
Inputs
V_IL
V_IH
I_LI
C_i
analog supply voltage (3.3 V)
3.1
digital supply voltage (3.3 V)
3.0
digital supply voltage (5 V)
4.75
analog supply current
note 1
−
digital supply current (3.3 V)
note 1
−
digital supply current (5 V)
note 1
−
LOW level input voltage
−0.5
(except SDA, SCL, AP, SP and XTALI)
HIGH level input voltage
2.0
(except LLC, SDA, SCL, AP, SP and XTALI)
HIGH level input voltage (LLC)
2.4
input leakage current
−
input capacitance
clocks
−
data
−
I/Os at high impedance −
3.5
V
3.6
V
5.25
V
110
mA
80
mA
10
mA
+0.8
V
V_DDD(5) + 0.5 V
V_DDD(5) + 0.5 V
1
µA
10
pF
8
pF
8
pF
Outputs
V_OL
LOW level output voltage
(except SDA and XTALO)
V_OH
HIGH level output voltage
(except LLC, SDA, and XTALO)
HIGH level output voltage (LLC)
I²C-bus; SDA and SCL
V_IL
LOW level input voltage
V_IH
HIGH level input voltage
I_i
input current
V_OL
LOW level output voltage (SDA)
I_o
output current
Clock timing (LLC)
T_LLC
δ
t_r
t_f
cycle time
duty factor t_HIGH/T_LLC
rise time
fall time
Input timing
t_SU;DAT
t_HD;DAT
input data set-up time (any other except
CDIR, SCL, SDA, RESET, AP and SP)
input data hold time (any other except
CDIR, SCL, SDA, RESET, AP and SP)
note 2
0
note 2
2.4
note 2
2.6
−0.5
3.0
V_i = LOW or HIGH
−10
I_OL = 3 mA
−
during acknowledge 3
note 3
34
note 4
40
note 3
−
note 3
−
6
3
0.6
V
V_DDD(5) + 0.5 V
V_DDD(5) + 0.5 V
+1.5
V
V_DDD(5) + 0.5 V
+10
µA
0.4
V
−
mA
41
ns
60
%
5
ns
6
ns
−
ns
−
ns
1996 Oct 02
34