SAA7182A Datasheet, PDF (18/45 Pages) NXP Semiconductors – Digital Video Encoder EURO-DENC2

Philips Semiconductors
Digital Video Encoder (EURO-DENC2)
Preliminary specification
SAA7182A; SAA7183A
Table 9 Subaddress 3A
DATA
BYTE
UV2C
Y2C
FMT16
DEMOFF
SYMP
PCREF
DISKEY
CBENB
LOGIC
LEVEL
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DESCRIPTION
Cb, Cr data are two’s complement.
Cb, Cr data are straight binary. Default after reset.
Y data is two’s complement.
Y data is straight binary. Default after reset.
Selects Cb, Y, Cr and Y on 8 lines on MP port (“CCIR 656” compatible). Default after reset.
Selects Cb and Cr on DP port and Y on MP port.
Y, Cb and Cr for RGB dematrix is active. Default after reset.
Y, Cb and Cr for RGB dematrix is bypassed.
Horizontal and vertical trigger is taken from RCV2 and RCV1 respectively. Default after reset.
Horizontal and vertical trigger is decoded out of “CCIR 656” compatible data at MP port.
Normal polarity of CREF for DIG-TV2 compatible input signals.
Inverted polarity of CREF for DIG-TV2 compatible input signals.
OVL keying enabled for Y, C and CVBS outputs. Default after reset.
OVL keying disabled for Y, C and CVBS outputs.
Data from input ports is encoded. Default after reset.
Colour bar with programmable colours (entries of OVL_LUTs) is encoded. The LUTs are read in
upward order from index 0 to index 7.
1996 Oct 02
18