SAA7182A Datasheet, PDF (37/45 Pages) NXP Semiconductors – Digital Video Encoder EURO-DENC2

Philips Semiconductors
Digital Video Encoder (EURO-DENC2)
Preliminary specification
SAA7182A; SAA7183A
handbook, _Lfu_Lll_Cpagewidth
CREF
MP(n)
DP(n)
RCV2
Y(0)
Cb(0)
Y(1)
Cr(0)
Y(2)
Cb(2)
Y(3)
Cr(2)
The data demultiplexing phase is coupled to the internal horizontal phase.
The CREF signal applies only for the 16 line digital TV format, because these signals are only valid in 13.5 MHz.
The phase of the RCV2 signal is programmed to tbf (tbf for 50 Hz) in this example in output mode (RCV2S).
Fig.17 Digital TV timing.
Y(4)
Cb(4)
MBE739
handbook, full pagewidth
H/L transition
count start
LOW
128
13
HPLL
increment
4 bits
reserved
0
21
RTCI
time slot: 0 1
14 19
not used in
SAA7182A/83A
FSCPLL increment (4)
sequence reserved (2)
5 bits ^{bit (1)} reset
reserved
bit (3)
0
valid invalid
sample sample
8/LLC
67 68
MGD673
(1) Sequence bit:
PAL = logic 0 then (R − Y) line normal; PAL = logic 1 then (R − Y) line inverted.
NTSC = logic 0 then no change.
(2) Reserved bits: 235 with 50 Hz systems; 232 with 60 Hz systems.
(3) Only from SAA7111 decoder.
(4) SAAA7111 provides (22 : 0) bits, resulting in 3 reserved bits before sequence bit.
Fig.18 RTCI timing.
1996 Oct 02
37