SAA7182A Datasheet, PDF (24/45 Pages) NXP Semiconductors – Digital Video Encoder EURO-DENC2

Philips Semiconductors
Digital Video Encoder (EURO-DENC2)
Preliminary specification
SAA7182A; SAA7183A
Table 22 Subaddress 67 to 6A
DATA BYTE⁽¹⁾
DESCRIPTION
L21O0
L21O1
L21E0
L21E1
first byte of captioning data, odd field
second byte of captioning data, odd field
first byte of extended data, even field
second byte of extended data, even field
Note
1. LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective
bytes have to carry the parity bit, in accordance with the definition of Line 21 encoding format.
Table 23 Subaddress 6B
DATA BYTE
PRCV2
ORCV2
CBLF
LOGIC LEVEL
DESCRIPTION
0
polarity of RCV2 as output is active HIGH, rising edge is taken when input,
respectively; default after reset
1
polarity of RCV2 as output is active LOW, falling edge is taken when input,
respectively
0
pin RCV2 is switched to input; default after reset
1
pin RCV2 is switched to output
0
if ORCV2 = HIGH, pin RCV2 provides an HREF signal (Horizontal Reference pulse
that is defined by RCV2S and RCV2E, also during vertical blanking Interval); default
after reset
if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal
synchronization only (if TRCV2 = 1); default after reset
1
if ORCV2 = HIGH, pin RCV2 provides a ‘Composite-Blanking-Not’ signal, this is a
reference pulse that is defined by RCV2S and RCV2E, excluding Vertical Blanking
Interval, which is defined by FAL and LAL
PRCV1
ORCV1
TRCV2
SRCV1
if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal
synchronization (if TRCV2 = 1) and as an internal blanking signal
0
polarity of RCV1 as output is active HIGH, rising edge is taken when input; default
after reset
1
polarity of RCV1 as output is active LOW, falling edge is taken when input
0
pin RCV1 is switched to input; default after reset
1
pin RCV1 is switched to output
0
horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from
decoded frame sync of CCIR 656 input (at bit SYMP = HIGH); default after reset
1
horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW)
−
defines signal type on pin RCV1; see Table 24
1996 Oct 02
24