SAA7182A Datasheet, PDF (22/45 Pages) NXP Semiconductors – Digital Video Encoder EURO-DENC2

Philips Semiconductors
Digital Video Encoder (EURO-DENC2)
Preliminary specification
SAA7182A; SAA7183A
Table 18 Subaddress 61:
DATA BYTE
FISE
PAL
SCBW
SECAM
YGS
INPI
DOWNA
DOWNB
LOGIC LEVEL
DESCRIPTION
0
864 total pixel clocks per line; default after reset
1
858 total pixel clocks per line
0
NTSC encoding (non-alternating V component)
1
PAL encoding (alternating V component); default after reset
0
enlarged bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 5 and 6); wide clipping for
SECAM
1
standard bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 5 and 6); default after reset
0
no SECAM encoding; default after reset
1
SECAM encoding activated
0
luminance gain for white − black 100 IRE; default after reset
1
luminance gain for white − black 92.5 IRE including 7.5 IRE set-up of black
0
PAL switch phase is nominal; default after reset
1
PAL switch phase is inverted compared to nominal
0
DACs for CVBS, Y and C in normal operational mode; default after reset
1
DACs for CVBS, Y and C forced to lowest output voltage
0
DACs for R, G and B in normal operational mode; default after reset
1
DACs for R, G and B forced to lowest output voltage
1996 Oct 02
22