SAA7182A Datasheet, PDF (26/45 Pages) NXP Semiconductors – Digital Video Encoder EURO-DENC2

Philips Semiconductors
Digital Video Encoder (EURO-DENC2)
Preliminary specification
SAA7182A; SAA7183A
Table 29 Logic levels and function of FLC
DATA BYTE
FLC1
0
0
1
1
FLC0
0
1
0
1
FUNCTION
interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset
non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
Table 30 Subaddress 6F
DATA BYTE LOGIC LEVEL
DESCRIPTION
CCEN
−
enables individual Line 21 encoding; see Table 31
TTXEN
0
disables teletext insertion
1
enables teletext insertion
SCCLN
−
selects the actual line, where closed caption or extended data are encoded
line = (SCCLN + 4) for M-systems
line = (SCCLN + 1) for other systems
Table 31 Logic levels and function of CCEN
DATA BYTE
CCEN1
0
0
1
1
CCEN0
0
1
0
1
FUNCTION
Line 21 encoding off
enables encoding in field 1 (odd)
enables encoding in field 2 (even)
enables encoding in both fields
Table 32 Subaddress 70 to 72
DATA BYTE
DESCRIPTION
RCV2S
start of output signal on RCV2 pin
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
first active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at
RCV2S = tbfH (tbfH)
RCV2E
end of output signal on RCV2 pin
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
last active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at
RCV2E = tbfH (tbfH)
1996 Oct 02
26