SAA7182A Datasheet, PDF (25/45 Pages) NXP Semiconductors – Digital Video Encoder EURO-DENC2

Philips Semiconductors
Digital Video Encoder (EURO-DENC2)
Preliminary specification
SAA7182A; SAA7183A
Table 24 Logic levels and function of SRCV1
DATA BYTE
SRCV11
0
0
1
SRCV10
0
1
0
1
1
AS OUTPUT AS INPUT
FUNCTION
VS
FS
FSEQ
not applicable
VS
FS
FSEQ
not applicable
vertical sync each field; default after reset
frame sync (odd/even)
field sequence, vertical sync every fourth field
(PAL = 0), eighth field (PAL = 1) or twelfth field
(SECAM = 1)
−
Table 25 Subaddress 6C and 6D
DATA BYTE
DESCRIPTION
HTRIG
sets the horizontal trigger phase related to signal on RCV1 or RCV2 input
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
increasing HTRIG decreases delays of all internally generated timing signals
reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV
used for triggering at HTRIG = tbf (tbf)
Table 26 Subaddress 6D
DATA BYTE LOGIC LEVEL
DESCRIPTION
VTRIG
−
sets the vertical trigger phase related to signal on RCV1 input
increasing VTRIG decreases delays of all internally generated timing signals,
measured in half lines
variation range of VTRIG = 0 to 31 (1FH)
Table 27 Subaddress 6E
DATA BYTE LOGIC LEVEL
DESCRIPTION
SBLBN
0
vertical blanking is defined by programming of FAL and LAL; default after reset
1
vertical blanking is forced in accordance with “CCIR 624” (50 Hz) or RS170A (60 Hz)
PHRES
−
selects the phase reset mode of the colour subcarrier generator; see Table 28
FLC
−
field length control; see Table 29
Table 28 Logic levels and function of PHRES
DATA BYTE
PHRES1
PHRES0
0
0
0
1
1
0
1
1
FUNCTION
no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset
reset every two lines or SECAM-specific if bit SECAM = 1
reset every eight fields
reset every four fields
1996 Oct 02
25