PLC18V8Z Datasheet, PDF (6/23 Pages) NXP Semiconductors – Zero standby power CMOS versatile PAL devices

Philips Semiconductors
Zero standby power
CMOS versatile PAL devices
Product specification
PLC18V8Z
OUTPUT MACRO CELL (OMC)
FROM AND
1
ARRAY
TO ALL OMCs
DIRECTION CONTROL TERM
V_CC
11
01 OE
00 ^MUX
10
{FROM
AND
ARRAY
S
X_{(n) OUTPUT}
D
Q
01
10 OUT
11 MUX
00
F
POLARITY
CLK
CONTROL
AC1_n
AC2_n
00
F ¹⁰
MUX ₁₁
01
NOTE:
Denotes a programmable cell location.
TO ALL OMCs
11 OE
THE OUTPUT MACRO CELL (OMC)
The PLC18V8Z series devices have 8 individually programmable
Output Macro Cells. The 72 AND inputs (or product terms) from the
programmable AND array are connected to the 8 OMCs in groups of
9. Eight of the AND terms are dedicated to logic functions; the ninth
is for asynchronous direction control, which enables/disables the
respective bidirectional I/O pin. Two product terms are dedicated for
the Synchronous Preset and Asynchronous Reset functions.
Each OMC can be independently programmed via 16 architecture
control bits, AC1_n and AC2_n (one pair per macro cell). Similarly,
each OMC has a programmable output polarity control bit (Xn). By
configuring the pair of architecture control bits according to the
configuration cell table, 4 different configurations may be
implemented. Note that the configuration cell is automatically
programmed based on the OMC configuration.
SP00014
DESIGN SECURITY
The PLC18V8Z series devices have a programmable security fuse
that controls the access to the data programmed in the device. By
using this programmable feature, proprietary designs implemented
in the device cannot be copied or retrieved.
1997 Aug 08
6