PLC18V8Z Datasheet, PDF (15/23 Pages) NXP Semiconductors – Zero standby power CMOS versatile PAL devices

Philips Semiconductors
Zero standby power
CMOS versatile PAL devices
Product specification
PLC18V8Z
LOGIC PROGRAMMING
The PLC18V8Z series is fully supported by industry standard
(JEDEC compatible) PLD CAD tools, including Philips
Semiconductors’ SNAP design software package. ABEL™ and
CUPL™ design software packages also support the PLC18V8Z
architecture.
All packages allow Boolean and state equation entry formats. SNAP,
ABEL and CUPL also accept, as input, schematic capture format.
PLC18V8Z logic designs can also be generated using the program
table entry format, which is detailed on the following pages. This
program table entry format is supported by SNAP only.
OUTPUT POLARITY – (O, B)
S
X
O, B
S
X
With Logic programming, the AND/OR/EX-OR gate input
connections necessary to implement the desired logic function are
coded directly from logic equations using the Program Table.
Similarly, various OMC configurations are implemented by
programming the Architecture Control bits AC1 and AC2. Note that
the configuration cell is automatically programmed based on the
OMC configuration.
In this table, the logic state of variables I, P and B associated with
each Sum Term S is assigned a symbol which results in the proper
fusing pattern of corresponding link pairs, defined as follows:
O, B
ACTIVE LEVEL
INVERTING¹
CODE
L
“AND” ARRAY – (I, B)
ACTIVE LEVEL
NON-INVERTING
CODE
H
SP00023
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
STATE
DON’T CARE
P
CODE
–
STATE
INACTIVE¹
P
CODE
O
STATE
I, B
P
CODE
H
NOTE:
1. A factory shipped unprogrammed device is configured such that all cells are in a conductive state.
STATE
I, B
P
CODE
L
SP00024
ABEL is a trademark of Data I/O Corp.
CUPL is a trademark of Logical Devices, Inc.
1997 Aug 08
15