PLC18V8Z Datasheet, PDF (16/23 Pages) NXP Semiconductors – Zero standby power CMOS versatile PAL devices

CF(XXXX)
NOTES:
In the unprogrammed or virgin state:
All AND gate locations are pulled to a logic “0” (Low).
Output polarity is inverting.
Pins 1 and 11 are configured as inputs 0 and 9, respectively, via
the configuration cell. The clock and OE functions are disabled.
All output macro cells (OMC) are configured as combinatorial I/O,
with the outputs disabled via the direction control term.
REV.
DATE
PROGRAM TABLE #
TOTAL NUMBER OF PARTS
CUSTOMER SYMBOLIZED PART #
PHILIPS DEVICE #
PURCHASE ORDER #
CUSTOMER NAME
VARIABLE
NAME