PLC18V8Z Datasheet, PDF (12/23 Pages) NXP Semiconductors – Zero standby power CMOS versatile PAL devices

Philips Semiconductors
Zero standby power
CMOS versatile PAL devices
Product specification
PLC18V8Z
POWER-UP RESET
In order to facilitate state machine design and testing, a power-up
reset function has been incorporated in the PLC18V8Z. All internal
registers will reset to Active-Low (logical “0”) after a specified period
of time (t_PPR). Therefore, any OMC that has been configured as a
registered output will always produce an Active-High on the
associated output pin because of the inverted output buffer. The
internal feedback (Q) of a registered OMC will also be set Low. The
programmed polarity of OMC will not affect the Active-High output
condition during a system power-up condition.
TIMING DIAGRAMS
INPUTS
I/O, REG.
ÉÉÉÉÉÉ _FEEDBACK
VALID INPUT
t_IS
t_IH
VALID INPUT
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ _tCKH
t_CKL
CLK
PIN 11 OE
t_CKP
t_CKO
t_OD2
t_OE2
REGISTERED
OUTPUTS
3–STATE
ANY INPUT
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ _{PROGRAMMED FOR}
DIRECTION CONTROL
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ _tPD
ÉÉÉÉÉÉÉÉ _{COMBINATORIAL}
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ OUTPUTS
t_OD1
Switching Waveforms
t_OE1
3-STATE
3.0V
4.5V
V_CC
ÉÉÉÉÉÉÉÉ _F
(OUTPUTS)
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ _{I, B}
ÉÉÉÉÉÉÉ _(INPUTS)
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ _CLK
t_PPR
1.5V
1.5V
t_CKL
t_IS
1.5V
t_CKO
1.5V
t_IH
1.5V
t_IS
1.5V
t_CKH
t_CKP
t_CKL
NOTE:
Diagram presupposes that the outputs (F) are enabled. The reset occurs regardless of the output condition (enabled or disabled).
Power-Up Reset
+5V
0V
V_OH
V_OL
+3V
0V
+3V
1.5V
0V
SP00020
1997 Aug 08
12