PLC18V8Z Datasheet, PDF (5/23 Pages) NXP Semiconductors – Zero standby power CMOS versatile PAL devices

Philips Semiconductors
Zero standby power
CMOS versatile PAL devices
Product specification
PLC18V8Z
LOGIC DIAGRAM
0
4
8
12
I0/CLK ¹
I1 ²
I2 ³
I3 ⁴
I4 ⁵
I5 ⁶
I6 ⁷
I7 ⁸
I8 ⁹
SP
AR
NOTES:
In the unprogrammed or virgin state:
All cells are in a conductive state.
All AND gate locations are pulled to a logic “0” (Low).
Output polarity is inverting.
16
20
24
28
32 35
CLK
DIR
SP
AC1
AC2
AR
19 _F7
CLK
OE
DIR
SP
AC1
AC2
AR
18 _F6
CLK
OE
DIR
SP
17 _F5
AC1
AC2
AR
CLK
OE
DIR
SP
16 _F4
AC1
AC2
AR
CLK
OE
DIR
SP
15 _F3
AC1
AC2
AR
CLK
OE
DIR
SP
14 _F2
AC1
AC2
AR
CLK
OE
DIR
SP
AC1
AC2
AR
13 _F1
CLK
OE
DIR
SP
AC1
AC2
AR
CLK
OE
12 _F0
CONFIG.
CELL
11 _I9/OE
Pins 1 and 11 are configured as Inputs 0 and 9, respectively, via the configuration cell. The clock and OE
functions are disabled.
All output macro cells (OMC) are configured as bidirectional I/O, with the outputs disabled via the direc-
tion term.
Denotes a programmable cell location.
SP00012
1997 Aug 08
5