PLC18V8Z Datasheet, PDF (10/23 Pages) NXP Semiconductors – Zero standby power CMOS versatile PAL devices

Philips Semiconductors
Zero standby power
CMOS versatile PAL devices
Product specification
PLC18V8Z
AC ELECTRICAL CHARACTERISTICS⁴
Commercial = 0°C ≤ T_amb ≤ +75°C, 4.75V ≤ V_CC < 5.25V;
Industrial = –40°C ≤ T_amb ≤ +85°C, 4.5V ≤ V_CC ≤ 5.5V; R₂ = 390Ω
TEST CONDITION¹
PLC18V8Z25
(Commercial)
PLC18V8ZIA
(Industrial)
SYMBOL
PARAMETER
FROM
TO
R₁ (Ω)
C_L
(pF)
MIN
MAX
MIN
MAX ^UNIT
Pulse width
t_CKP
Clock period
(Minimum t_IS + t_CKO)
CLK + CLK +
200
50
33
33
ns
t_CKH
Clock width High
CLK + CLK –
200
50
15
15
ns
t_CKL
Clock width Low
CLK – CLK +
200
50
15
15
ns
t_ARW
Async reset pulse width
I ±, F± I +, F +
25
25
ns
Hold time
t_IH
Input or feedback
data hold time
CLK + Input ±
200
50
0
0
ns
Setup time
t_IS
Input or feedback
data setup time
I ±, F± CLK +
200
50
18
18
ns
Propagation delay
t_PD
Delay from input
to active output
I ±, F±
F±
200
50
25
25
ns
t_CKO
Clock High to output valid
access Time
CLK +
F±
200
50
15
15
ns
t_OE13
Product term enable to
outputs off
I ±, F±
F±
Active-High R = 1.5k
Active-Low R = 550
50
25
25
ns
t_OD12
Product term disable to
outputs off
I ±, F±
F±
From V_OH R = ∞
From V_OL R = 200
5
25
t_OD22
Pin 11 output disable High
to outputs off
OE –
F±
From V_OH R = ∞
From V_OL R = 200
5
20
t_OE23
Pin 11 output enable to
active output
OE +
F±
Active-High R = 1.5k
Active-Low R = 550
50
20
25
ns
20
ns
20
ns
t_ARD
Async reset delay
t_ARR
Async reset recovery time
t_SPR
Sync preset recovery time
t_PPR
Power-up reset
Frequency of operation
I ±, F±
I ±, F±
I ±, F±
V_CC +
F+
CLK +
CLK +
F+
30
30
ns
20
20
ns
20
20
ns
25
25
ns
f_MAX
Maximum frequency
I/(t_IS + t_CKO)
200
50
30
30 MHz
NOTES:
1. Refer also to AC Test Conditions. (Test Load Circuit)
2. For 3-State output; output enable times are tested with C_L = 50pF to the 1.5V level, and S₁ is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with C_L = 5pF. High-to-High impedance tests are made to an output
voltage of V_T = (V_OH – 0.5V) with S₁ open, and Low-to-High impedance tests are made to the V_T = (V_OL + 0.5V) level with S₁ closed.
3. Resistor values of 1.5k and 550Ω provide 3-State levels of 1.0V and 2.0V, respectively. Output timing measurements are to 1.5V level.
4. Leave all the cells on unused product terms intact (unprogrammed) for all patterns.
1997 Aug 08
10