TDA4855 Datasheet, PDF (22/44 Pages) NXP Semiconductors – Autosync Deflection Controller ASDC

Philips Semiconductors
Autosync Deflection Controller (ASDC)
Preliminary specification
TDA4855
15. The superimposed logarithmic parabola at EWTRP (pin 20) tracks with internal VGA settings and with VPOS, but
not with VAMP settings (see Fig.17).
16. If f_H tracking is enabled, the amplitude of the complete EWDRV output signal (parabola + DC shift + trapezium) will
be changed proportional to I_HREF. The EWDRV low level of 1.2 V remains fixed.
17. First pole of transconductance amplifier is 5 MHz without external capacitor (will become the second pole, if the OTA
operates as an integrator).
18. Open-loop gain is -VV----^B-_B--^O-_I--_N-^P- at f = 0 with no resistive load and C_BOP = 4.7 nF (from BOP (pin 3) to GND).
Vertical and EW adjustments
handbo_Io_Vk,_Oh_Ual_Tfp₁age
IVOUT2
MBG590
handboo_Vk_E, h_Wal_Dfp_Rag_Ve
∆l2 ∆l1⁽¹⁾
MBG591
VPAR(EWDRV)
t
(1) ∆I₁ is the maximum amplitude setting at VAMP (pin 18);
VGA presets disabled, VPOS centred and VSCOR = 0%.
∆VAMP = ^∆∆----II--²¹- × 100%
Fig.3 I_VOUT1 and I_VOUT2 as functions of time.
t
∆EWPAR = 0 to V_PAR(EWDRV).
Fig.4 V_EWDRV as a function of time.
1996 Jul 18
22