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TDA4855 Datasheet, PDF (15/44 Pages) NXP Semiconductors – Autosync Deflection Controller ASDC
Philips Semiconductors
Autosync Deflection Controller (ASDC)
Preliminary specification
TDA4855
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP.
PLL1 phase comparator and frequency-locked loop [HPLL1 (pin 26) and HBUF (pin 27)]
tHSYNC(max)
maximum width of horizontal fH < 45 kHz; note 3
−
−
sync pulse (referenced to line fH > 45 kHz; note 3
−
−
period)
tlock(HPLL1)
VHPLL1
VHBUF
Iload(HBUF)
total lock-in time of PLL1
control voltage
buffered f/v voltage at HBUF
(pin 27)
maximum load current
notes 4 and 5
fH(min); note 6
fH(max); note 6
−
40
−
5.6
−
2.5
−
−
ADJUSTMENT OF HORIZONTAL PICTURE POSITION
∆HPOS
horizontal shift adjustment
IHSHIFT = 0
range (referenced to horizontal IHSHIFT = −135 µA
period)
−
−10.5
−
+10.5
IHPOS
input current
∆HPOS = +10.5%
∆HPOS = −10.5%
−110
−
−120
0
Vref(HPOS)
Voff(HPOS)
reference voltage at input
note 7
picture shift is centred if HPOS
(pin 30) is forced to ground
−
5.1
0
−
Horizontal oscillator [HCAP (pin 29) and HREF (pin 28)]
fH(0)
∆fH(0)
free-running frequency without
PLL1 action (for testing only)
spread of free-running
frequency (excluding spread of
external components)
RHBUF = ∞;
RHREF = 2.4 kΩ;
CHCAP = 10 nF; note 5
TC
temperature coefficient of
free-running frequency
fH(max)
VHREF
maximum oscillator frequency
voltage at input for reference
current
30.53 31.45
−
−
−100 0
−
−
2.43 2.55
PLL2 phase detector [HFLB (pin 1) and HPLL2 (pin 31)]
∆φPLL2
PLL2 control (advance of
maximum advance
horizontal drive with respect to minimum advance
middle of horizontal flyback)
36
−
−
7
td(HFLB)
delay between middle of
HPOS (pin 30) grounded −
200
horizontal sync and middle of
horizontal flyback
VPROT(HPLL2)
maximum voltage for PLL2
protection mode/soft start
−
4.4
Icharge(HPLL2)
charge current for external
capacitor during soft start
VHPLL2 < 3.7 V
−
15
MAX.
20
25
80
−
−
−4.0
−
−
−135
−
−
0.1
32.39
±3.0
+100
130
2.68
−
−
−
−
−
UNIT
%
%
ms
V
V
mA
%
%
µA
µA
V
V
kHz
%
10−6/K
kHz
V
%
%
ns
V
µA
1996 Jul 18
15