TDA4855 Datasheet, PDF (14/44 Pages) NXP Semiconductors – Autosync Deflection Controller ASDC

Philips Semiconductors
Autosync Deflection Controller (ASDC)
Preliminary specification
TDA4855
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP.
VERTICAL SYNC OUTPUT AT VSYNC (PIN 14) DURING COMPOSITE SYNC AT HSYNC (PIN 15)
I_VSYNC
output current
during internal vertical
−0.7
−1.0
sync
V_VSYNC
internal clamping voltage level during internal vertical 4.4
4.8
sync
steepness of slopes
−
300
Automatic polarity correction for vertical sync
t_VSYNC(max)
maximum width of vertical sync
pulse
t_d(VPOL)
delay for changing polarity
Video clamping/vertical blanking output [CLBL (pin 16)]
−
−
0.3
−
t_clamp(CLBL)
V_clamp(CLBL)
t_d(clamp)
t_clamp(max)
TC_clamp
V_blank(CLBL)
t_blank(CLBL)
TC_blank
V_scan(CLBL)
TC_scan
I_sink(CLBL)
I_load(CLBL)
width of video clamping pulse measured at V_CLBL = 3 V 0.6
0.7
top voltage level of video
4.32 4.75
clamping pulse
delay between trailing edge of clamping pulse triggered −
130
horizontal sync and start of
on trailing edge of
video clamping pulse
horizontal sync
maximum duration of video
measured at V_CLBL = 3 V −
−
clamping pulse referenced to
end of horizontal sync
temperature coefficient of
−
+4
V_clamp(CLBL)
steepness of slopes for
clamping pulse
R_L = 1 MΩ; C_L = 20 pF −
50
top voltage level of vertical
blanking pulse
notes 1 and 2
1.7
1.9
width of vertical blanking pulse VGA presets active
500
575
VGA presets disabled
240
300
temperature coefficient of
V_blank(CLBL)
output voltage during vertical
scan
I_CLBL = 0
−
+2
0.59 0.63
temperature coefficient of
V_scan(CLBL)
internal sink current
−
−2
2.4
−
external load current
−
−
MAX.
−1.35
5.2
−
300
1.8
0.8
5.23
−
1.0
−
−
2.1
650
360
−
0.67
−
−
−3.0
UNIT
mA
V
ns/mA
µs
ms
µs
V
ns
µs
mV/K
ns/V
V
µs
µs
mV/K
V
mV/K
mA
mA
1996 Jul 18
14