TDA4855 Datasheet, PDF (21/44 Pages) NXP Semiconductors – Autosync Deflection Controller ASDC

Philips Semiconductors
Autosync Deflection Controller (ASDC)
Preliminary specification
TDA4855
Notes to the characteristics
1. For duration of vertical blanking pulse see characteristics of “Vertical oscillator (oscillator frequency in application
without adjustment of free-running frequency fv(o))”.
2. Continuous blanking at CLBL (pin 16) will be activated, if one of the following conditions is true:
a) No horizontal flyback pulses at HFLB (pin 1) within a line
b) X-ray protection is triggered
c) Voltage at HPLL2 (pin 31) is low (for soft start of horizontal drive)
d) Supply voltage at V_CC (pin 9) is low
e) PLL1 unlocked while frequency-locked loop is in search mode.
3. To ensure safe locking of the horizontal oscillator, one of the following procedures is required:
a) Search mode starts always from f_min. Then the PLL1 filter components are a 3.3 nF capacitor from pin 26 to
ground in parallel with an 8.2 kΩ resistor in series with a 47 nF capacitor.
b) Search mode starts either from f_min or f_max with HPOS in middle position (I_HPOS = 60 µA). Then the PLL1 filter
components are a 1.5 nF capacitor from pin 26 to ground in parallel with a 27 kΩ resistor in series with a 47 nF
capacitor.
c) After locking is achieved, HPOS can be operated in the normal way.
4. Loading of HPLL1 (pin 26) is not allowed.
5. Oscillator frequency is f_min when no sync input signal is present (no continuous blanking at pin 16).
6. Voltage at HPLL1 (pin 26) is fed to HBUF (pin 27) via a buffer. Disturbances caused by horizontal sync are removed
by an internal sample-and-hold circuit.
7. Input resistance at HPOS (pin 30): R_HPOS = ^k--q-T--- × -I-_H----_P-1--_O----_S--
8. Full vertical sync range with constant amplitude (f_V(min) : f_V(max) = 1 : 2.5) can be made usable by choosing an
application with adjustment of free-running frequency.
9. If higher vertical frequencies are required, sync range can be shifted by using a smaller capacitor at VCAP (pin 24).
10. Value of resistor at VREF (pin 23) may not be changed.
11. All vertical and EW adjustments are specified at nominal vertical settings, which means:
a) ∆VAMP = 100% (I_VAMP = 135 µA)
b) ∆VSCOR = 0 (pin 19 open-circuit)
c) ∆VPOS centred (pin 17 forced to ground)
d) VGA presets disabled (current ratio I_HBUF : I_HREF < 2.25)
e) f_H = 70 kHz.
12. VGA presets are enabled below the horizontal frequency at which the current ratio I_HBUF : I_HREF exceeds the
specified value.
13. The superimposed logarithmic sawtooth at VSCOR (pin 19) tracks with internal VGA settings and with VPOS, but
not with VAMP settings. The superimposed waveform is described by ^k--q--T-- × In1-1----_+–-----dd-- with ‘d’ being the modulation
depth of a sawtooth from −⁵⁄₆ to +⁵⁄₆. A linear sawtooth with the same modulation depth can be recovered in an
external long-tailed pair (see Fig.17).
14. The output signal at EWDRV (pin 11) may consist of parabola + DC shift + trapezium correction. These adjustments
have to be carried out in a correct relationship to each other in order to avoid clipping due to the limited output voltage
range at EWDRV.
1996 Jul 18
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