TDA4855 Datasheet, PDF (13/44 Pages) NXP Semiconductors – Autosync Deflection Controller ASDC

Philips Semiconductors
Autosync Deflection Controller (ASDC)
Preliminary specification
TDA4855
CHARACTERISTICS
V_CC = 12 V; T_amb = 25 °C; peripheral components in accordance with Fig.1; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Horizontal sync separator
INPUT CHARACTERISTICS FOR DC-COUPLED TTL SIGNALS [HSYNC (PIN 15)]
V_DC(HSYNC)
sync input signal voltage
slicing voltage level
1.7
−
−
V
1.2
1.4
1.6
V
t_r(HSYNC)
t_f(HSYNC)
t_W(HSYNC)
I_DC(HSYNC)
rise time of sync pulse
fall time of sync pulse
minimum width of sync pulse
input current
V_HSYNC = 0.8 V
V_HSYNC = 5.5 V
10
−
10
−
0.7
−
−
−
−
−
500
ns
500
ns
−
µs
−200 µA
10
µA
INPUT CHARACTERISTICS FOR AC-COUPLED VIDEO SIGNALS (SYNC-ON-VIDEO, NEGATIVE SYNC POLARITY)
V_AC(HSYNC)
sync amplitude of video input
signal voltage
−
300
−
mV
slicing voltage level
source resistance
90
(measured from top sync)
R_S = 50 Ω
V_clamp(HSYNC)
top sync clamping voltage level
1.1
I_C(HSYNC)
charge current for coupling
capacitor
V_HSYNC > V_clamp(HSYNC)
1.7
120
150
mV
1.28 1.5
V
2.4
3.4
µA
t_HSYNC(min)
R_S(max)
r_diff(HSYNC)
minimum width of sync pulse
maximum source resistance
differential input resistance
duty factor = 7%
during sync
0.7
−
−
−
−
80
−
µs
1500 Ω
−
Ω
Automatic polarity correction for horizontal sync
t--_{P---t-(-H-H----)-}
horizontal sync pulse width
related to t_H
f_H < 45 kHz
f_H > 45 kHz
−
−
20
%
−
−
25
%
t_P(H)
delay time for changing polarity
0.3
−
1.8
ms
Vertical sync integrator
t_int(V)
integration time for generation
of a vertical trigger pulse
f_H = 31.45 kHz;
I_HREF = 1.052 mA
f_H = 64 kHz;
I_HREF = 2.141 mA
f_H = 100 kHz;
I_HREF = 3.345 mA
7
10
13
µs
3.9
5.7
6.5
µs
2.5
3.8
4.5
µs
Vertical sync slicer (DC-coupled, TTL compatible) [VSYNC (pin 14)]
V_VSYNC
sync input signal voltage
slicing voltage level
1.7
−
−
V
1.2
1.4
1.6
V
I_VSYNC
input current
0 V < V_SYNC < 5.5 V
−
−
±10
µA
1996 Jul 18
13