74HC7030 Datasheet, PDF (21/22 Pages) NXP Semiconductors – 9-bit x 64-word FIFO register; 3-state

Philips Semiconductors
9-bit x 64-word FIFO register; 3-state
Product specification
74HC/HCT7030
Sequence 1 (Both FIFOs empty, starting shift-in process):
After a MR pulse has been applied FIFO_A and FIFO_B are empty. The DOR flags of FIFO_A and FIFO_B go
LOW due to no valid data being present at the outputs. The DIR flags are set HIGH due to the FIFOs being
ready to accept data. SO_B is held HIGH and two SI_A pulses are applied (1). These pulses allow two data
words to ripple through to the output stage of FIFO_A and to the input stage of FIFO_B (2). When data arrives
at the output of FIFO_B, a DOR_B pulse is generated (3). When SO_B goes LOW, the first bit is shifted out and
a second bit ripples through to the output after which DOR_B goes HIGH (4).
Sequence 2 (FIFO_B runs full):
After the MR pulse, a series of 64 SI pulses are applied. When 64 words are shifted in, DIR_B remains LOW
due to FIFO_B being full (5). DOR_A goes LOW due to FIFO_A being empty.
Sequence 3 (FIFO_A runs full):
When 65 words are shifted in, DOR_A remains HIGH due to valid data remaining at the output of FIFO_A.
Q_nA remains HIGH, being the polarity of the 65th data word (6). After the 128th SI pulse, DIR remains LOW
and both FIFOs are full (7). Additional pulses have no effect.
Sequence 4 (Both FIFOs full, starting shift-out process):
SI_A is held HIGH and two SO_B pulses are applied (8). These pulses shift out two words and thus allow two
empty locations to bubble-up to the input stage of FIFO_B, and proceed to FIFO_A (9). When the first empty
location arrives at the input of FIFO_A, a DIR_A pulse is generated (10) and a new word is shifted into FIFO_A.
SI_A is made LOW and now the second empty location reaches the input stage of FIFO_A, after which
DIR_A remains HIGH (11).
Sequence 5 (FIFO_A runs empty):
At the start of sequence 5 FIFO_A contains 63 valid words due to two words being shifted out and one word
being shifted in in sequence 4. An additional series of SO_B pulses are applied. After 63 SO_B pulses, all
words from FIFO_A are shifted into FIFO_B. DOR_A remains LOW (12).
Sequence 6 (FIFO_B runs empty):
After the next SO_B pulse, DIR_B remains HIGH due to the input stage of FIFO_B being empty (13). After
another 63 SO_B pulses, DOR_B remains LOW due to both FIFOs being empty (14). Additional SO_B pulses
have no effect. The last word remains available at the output Q_n.
Fig.22 Waveforms showing the functionality and intercommunication between two FIFOs (refer to Fig.19).
December 1990
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