74HC7030 Datasheet, PDF (12/22 Pages) NXP Semiconductors – 9-bit x 64-word FIFO register; 3-state

Philips Semiconductors
9-bit x 64-word FIFO register; 3-state
AC WAVEFORMS
Shifting in sequence FIFO empty to FIFO full
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.6 Waveforms showing the SI input to DIR output propagation
delay. The SI pulse width and SI maximum pulse frequency.
With FIFO full; SI held HIGH in anticipation of empty location
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.7 Waveforms showing bubble-up delay, SO input to DIR output
and DIR output pulse width.
December 1990
12
Product specification
74HC/HCT7030
Notes to Fig.6
1. DIR initially HIGH; FIFO is
prepared for valid data.
2. SI set HIGH; data loaded into
input stage.
3. DIR drops LOW, input stage
“busy”.
4. SI set LOW; data from first
location “ripple through”.
5. DIR goes HIGH, status flag
indicates FIFO prepared for
additional data.
6. Repeat process to load 2nd word
through to 64th word into FIFO.
7. DIR remains LOW; with attempt
to shift into full FIFO, no data
transfer occurs.
Notes to Fig.7
1. FIFO is initially full, shift-in is held
HIGH.
2. SO pulse; data in the output
stage is unloaded, “bubble-up
process of empty locations
begins”.
3. DIR HIGH; when empty location
reached input stage, flag
indicates FIFO is prepared for
data input.
4. DIR returns to LOW; FIFO is full
again.
5. SI brought LOW; necessary to
complete shift-in process, DIR
remains LOW, because FIFO is
full.