74HC7030 Datasheet, PDF (20/22 Pages) NXP Semiconductors – 9-bit x 64-word FIFO register; 3-state

Philips Semiconductors
9-bit x 64-word FIFO register; 3-state
Product specification
74HC/HCT7030
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.21 FIFO to FIFO communication; output timing under full condition.
Notes to Fig.21
1. FIFO_A and FIFO_B initially full,
SI_B held HIGH in anticipation of
shifting in new data as empty
location bubbles-up.
2. Unload one word from FIFO_B;
SO pulse applied, results in DOR
pulse.
3. DIR_B and SO_A pulse HIGH;
(bubble-up delay after SO_B LOW)
data is loaded into FIFO_B as a
result of the DIR pulse, data is
shifted out of FIFO_A.
4. DOR_A and SI_B go LOW; flag
indicates the output stage of
FIFO_A is busy, shift-in to FIFO_B is
complete.
5. DOR_A and SI_B go HIGH; flag
indicates valid data is again
available at FIFO_A output stage,
SI_B is held HIGH, awaiting
bubble-up of empty location.
6. DIR_A goes HIGH; (bubble-up
delay after SO_A LOW) an empty
location is present at input stage
of FIFO_A.
December 1990
20