74HC7030 Datasheet, PDF (19/22 Pages) NXP Semiconductors – 9-bit x 64-word FIFO register; 3-state

Philips Semiconductors
9-bit x 64-word FIFO register; 3-state
Product specification
74HC/HCT7030
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.20 FIFO to FIFO communication; input timing under empty condition.
Notes to Fig.20
1. FIFO_A and FIFO_B initially empty,
SO_A held HIGH in anticipation of
data.
2. Load one word into FIFO_A; SI
pulse applied, results in DIR
pulse.
3. Data out _A/data in _B transition;
valid data arrives at FIFO_A output
stage after a specified delay of
the DOR flag, meeting data input
set-up requirements of FIFO_B.
4. DOR_A and SI_B pulse HIGH;
(ripple through delay after
SI_A LOW) data is unloaded from
FIFO_A as a result of the data
output ready pulse, data is shifted
into FIFO_B.
5. DIR_B and SO_A go LOW; flag
indicates input stage of FIFO_B is
busy, shift-out of FIFO_A is
complete.
6. DIR_B and SO_A go HIGH
automatically; the input stage of
FIFO_B is again able to receive
data, SO is held HIGH in
anticipation of additional data.
7. DOR_B goes HIGH; (ripple through
delay after SI_B LOW) valid data is
present one propagation delay
later at the FIFO_B output stage.
December 1990
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