74HC7030 Datasheet, PDF (13/22 Pages) NXP Semiconductors – 9-bit x 64-word FIFO register; 3-state

Philips Semiconductors
9-bit x 64-word FIFO register; 3-state
Master reset applied with FIFO full
Product specification
74HC/HCT7030
Notes to Fig.8
1. DIR LOW, output ready HIGH;
assume FIFO is full.
2. MR pulse LOW; clears FIFO.
3. DIR goes HIGH; flag indicates
input prepared for valid data.
4. DOR drops LOW; flag indicates
FIFO empty.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.8 Waveforms showing the MR input to DIR, DOR output
propagation delays and the MR pulse width.
Shifting out sequence; FIFO full to FIFO empty
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.9 Waveforms showing the SO input to DIR output propagation
delay. The SO pulse width and SO maximum pulse frequency.
Notes to Fig.9
1. DOR HIGH; no data transfer in
progress, valid data is present at
output stage.
2. SO set HIGH; results in DOR
going LOW.
3. DOR drops LOW; output stage
“busy”.
4. SO is set LOW; data in the input
stage is unloaded, and new data
replaces it as empty location
“bubbles-up” to input stage.
5. DOR goes HIGH; transfer
process completed, valid data
present at output after the
specified propagation delay.
6. Repeat process to unload the 3rd
through to the 64th word from
FIFO.
7. DOR remains LOW; FIFO is
empty.
December 1990
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