TDA8007B Datasheet, PDF (17/36 Pages) NXP Semiconductors – Double multiprotocol IC card interface

Philips Semiconductors
Double multiprotocol IC card interface
Product specification
TDA8007B
For other baud rates than those given in Table 15, there
is the possibility to set bit CKU (clock UART) to logic 1. In
this case, the ETU will last half of the formula given
above.
If bit AUTOCONV is set, then the convention is set by
software using bit CONV in the UART Configuration
Register. If it is reset, then the configuration is
automatically detected on the first received character
whilst the Start Session (SS) bit is set.
Synchronous/Asynchronous (SAN) is set by software if a
synchronous card is expected. The UART is then
bypassed, and only bit 0 in the URR and UTR is
connected to the I/O. In this case the CLK is controlled by
bit SC in the CCR.
When Power-down mode (PDWN) is set by software, the
crystal oscillator is stopped. This mode allows low
consumption in applications where it is required. During
this mode, it is not possible to select another card other
than the currently selected one. There are 5 ways of
escaping from the Power-down mode:
1. Insert card 1 or card 2
2. Withdraw card 1 or card 2
3. Select the TDA8007B by resetting CS (this assumes
that the TDA8007B had been deselected after setting
Power-down mode)
4. INTAUXL has been set due to a change on pin
INTAUX
5. If CS is permanently set to LOW, reset bit PDWN by
software.
After any of these 5 events, the TDA8007B will leave the
Power-down mode, and will pull INT LOW when it is ready
to communicate with the system microcontroller. The
system microcontroller may then read the status
registers, and INT will return HIGH (if the system
microcontroller has woken the TDA8007B by reselecting
it, then no bits will be set in the status registers).
If the Disable AUX (DISAUX) interrupt bit in UCR2 is set,
then a change on INTAUX will not generate an interrupt
(but bit INTAUXL in the HSR will be set; it is therefore
necessary to read the HSR before a DISAUX reset to
avoid an interrupt by INTAUXL). To avoid an interrupt
during a change of card, it is better to set the DISAUX bit
in UCR2 for both cards.
If the Disable TBE/RBF (DISTBE/RBF) interrupt bit is set,
then reception or transmission of a character will not
generate an interrupt:
• This feature is useful for increasing communication
speed with the card; in this case, a copy of the
TBE/RBF bit within the MSR must be polled (and not
the original) in order not to loose priority interrupts
which can occur in the USR.
• The Guard Time Register (see Table 17) is used for
storing the number of guard ETUs given by the card
during ATR. In transmission mode, the UART will wait
this number of ETUs before transmitting the character
stored in the UTR. In T = 1 protocol, when GTR = FF
means operation at 11 ETUs. In protocol T = 0,
GTR = FF means operation at 12 ETUs.
• The UART Configuration Register (see Table 18) is
used for setting the parameters of the ISO UART.
The Convention (CONV) bit is set if the convention is
direct. CONV is either automatically written by hardware
according to the convention detected during ATR, or by
software if the bit AUTOCONV is set.
The SS bit is set before ATR for automatic convention
detection and early answer detection (this bit must be
reset by software after reception of a correct initial
character).
The Last Character to Transmit (LCT) bit is set by
software before writing the last character to be
transmitted in the UTR. It allows automatic change to
reception mode. It is reset by hardware at the end of a
successful transmission.
The Transmit/Receive (T/R) bit is set by software for
transmission mode. A change from logic 0 to logic 1 will
set bit TBE in the USR. Bit T/R is automatically reset by
hardware if the LCT bit has been used before transmitting
the last character.
The Protocol (PROT) bit is set if the protocol type is
asynchronous T = 1. If PROT = 0, the protocol is T = 0.
The Flow Control (FC) bit is set if flow control is used (not
described in this specification).
If the Force Inverse Parity (FIP) bit is set to HIGH the
UART will NAK a correctly received character, and will
transmit characters with wrong parity bits.
2000 Nov 09
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