TDA8007B Datasheet, PDF (16/36 Pages) NXP Semiconductors – Double multiprotocol IC card interface

Philips Semiconductors
Double multiprotocol IC card interface
Product specification
TDA8007B
CARD REGISTERS
When cards 1 2 or 3 are selected, then the following registers may be used for programming some specific parameters.
The Programmable Divider Register (see Table 13) is used for counting the cards clock cycles forming the ETU. It is an
auto-reload 8-bit counter decounting from the programmed value down to 0.
Table 13 Programmable Divider Register (PDR1, 2 and 3) (read and write); address: 2 (all bits are cleared after reset)
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
The UART Configuration Register 2 bits are given in Table 14. If bit PSC is set to logic 1, then the prescaler value is 32.
If bit PSC is set to logic 0, then the prescaler value is 31. One ETU will last a number of card clock cycles equal to
prescaler x PDR. All baud rates specified in ISO 7816 norm are achievable with this configuration.
Table 14 UART configuration register 2 (UCR21, 22 and 23) (read and write); address: 3
(all relevant bits are cleared after reset)
UC27
UC26
not used DISTBE/RBF
UC25
DISAUX
UC24
PDWN
UC23
SAN
UC22
AUTOCONV
UC21
CKU
UC20
PSC
Table 15 Baud rates with a 3.58 MHz card clock frequency (31;12 means prescaler set to 31 and PDR set to 12)
F
D
0
1
2
3
4
5
6
9
10
11
12
13
1
31;12 31;12 31;18 31;24 31;36 31;48 31;60 32;16 32;24 32;32 32;48 32;64
9600 9600 6400 4800 3200 2400 1920
2
31;6 31;6 31;9 31;12 31;18 31;24 31;30 32;8 32;12 32;16 32;24 32;32
19200 19200 12800 9600 6400 4800 3840
3
31;3 31;3
31;6 31;9 31;12 31;15 32;4 32;6 32;8 32;12 32;16
38400 38400
19200 12800 9600 7680
4
31;3
31;6
32;2 32;3 32;4 32;6 32;8
38400
19200
5
31;3
32;1
32;2 32;3 32;4
38400
6
32;1
32;2
8
31;1 31;1
31;2 31;3 31;4 31;5
32;2
32;4
115200 115200
57600 38400 28800 23040
9
31;3
38400
2000 Nov 09
16