TDA8007B Datasheet, PDF (15/36 Pages) NXP Semiconductors – Double multiprotocol IC card interface

Philips Semiconductors
Double multiprotocol IC card interface
Product specification
TDA8007B
Overrun (OVR) is HIGH if the UART has received a new
character whilst the FIFO was full. In this case, at least one
character has been lost.
In protocol T = 0: Parity Error (PE) is HIGH if the UART has
detected a number of received characters with parity
errors equal to the number written in PEC2, PEC1 and
PEC0 or if a transmitted character has been NAKed by the
card.
In protocol T = 0: a character received with a parity error is
not stored in the FIFO (the card is supposed to repeat this
character).
In protocol T = 1: a character with a parity error is stored in
the FIFO and the parity error counter is not active.
Early Answer (EA) is HIGH if the first start bit on the I/O
during ATR has been detected between 200 and 384 CLK
pulses (all activities on the I/O during the 200 first CLK
pulses with RST LOW or HIGH are not taken into account).
These 2 features are reinitialized at each toggling of RST.
Bit TO1 is set when counter 1 has reached its terminal
count.
Bit TO3 is set when counter 3 has reached its terminal
count.
If any of the status bits FER, OVR, PE, EA, TO1 or TO3
are set then INT will go LOW. The bit having caused the
interrupt is reset at the end of a read operation of the USR.
If TBE/RBF is set, and if the mask bit DISTBE/RBF within
USR2 is not set, then INT will also be LOW. TBE/RBF is
reset when data has been written to the UTR, when data
has been read from the URR, or when changing from
transmission mode to reception mode.
Table 8 UART transmit register (write only); address: D (all bits are cleared after reset)
UT7
UT6
UT5
UT4
UT3
UT2
UT1
UT0
UT7
UT6
UT5
UT4
UT3
UT2
UT1
UT0
Table 9 UART receive register (read only); address: D (all bits are cleared after reset)
UR7
UR7
UR6
UR6
UR5
UR5
UR4
UR4
UR3
UR3
UR2
UR2
UR1
UR1
UR0
UR0
Table 10 Mixed status register (read only); address: C
(bits TBE, RBF and BGT are cleared after reset; bit FE is set after reset)
MS7
not used
MS6
FE
MS5
BGT
MS4
not used
MS3
PR2
MS2
PR1
MS1
INTAUX
MS0
TBE/RBF
Table 11 FIFO control register (write only); address: C (all relevant bits are cleared after reset)
FC7
FC6
FC5
FC4
FC3
FC2
FC1
FC0
not used
PEC2
PEC1
PEC0
not used
FL2
FL1
FL0
Table 12 UART status register (read only); address: E (all bits are cleared after reset)
US7
US6
US5
US4
US3
US2
TO3
not used
TO1
EA
PE
OVR
US1
FER
US0
TBE/RBF
2000 Nov 09
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