PI2EQX5864 Datasheet, PDF (9/18 Pages) Pericom Semiconductor Corporation – 5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis, &I2C Control

PI2EQX5864
5.0Gbps 4-Lane PCI Express GenII Re-Driver
with Equalization, Emphasis and I²C Control
BYTE 5 - Channel Reset (RESET)
RES_xy# =0=reset, RES_xy# =1=normal operation. Latch from RES_A# & RES_B# inputs at startup
Bit
7
6
5
4
3
2
1
Name RES_A0# RES_B0# RES_A1# RES_B1# RES_A2# RES_B2# RES_A3#
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
1
1
1
1
1
1
1
State
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
0
RES_B3#
R/W
1
The Channel Reset register allows for restart of an individual channels Receiver Detect function. A transition from 0 to 1 initiates a
new Receiver Detect cycle (if the channel is enabled and receiver detect is enabled). While static at 0 or 1, the RES_zy# bit will have
no effect on operation. The Channel Reset bits are read/write allowing the current state to be checked.
BYTE 6 - Power Down Control (PWR)
PD_xy# =0=channel off/power down, PD_xy# =1=normal operation, Latch from PD# input at startup
Bit
7
6
5
4
3
2
Name
PD_A0# PD_B0# PD_A1# PD_B1# PD_A2# PD_B2#
Type
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
1
1
1
1
1
1
State
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
1
PD_A3#
R/W
1
0
PD_B3#
R/W
1
The Power Down Control register allows for individual control over each channel for power savings. When PD_xy# is logic 0 the
channel is turned off. When PD_xy# is 1 then the channel is enabled for normal operation.
BYTE 7 - Receiver Detect Enable (RXD)
RXD_xy =0=channel off/power down, RXD_xy =1=normal operation, Latch from PD# input at startup
Bit
7
6
5
4
3
2
Name
RXD_A0 RXD_B0 RXD_A1 RXD_B1 RXD_A2 RXD_B2
Type
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
1
1
1
1
1
1
State
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
1
RXD_A3
R/W
1
0
RXD_B3
R/W
1
The Receiver Detect Enable register allows for control of the receiver detect state machine for each individual channel. When
RXD_xy is set to 0, then the receiver detect function is disabled. When RXD_xy is logic 1, then the receiver detect state machine is
enabled for operation. The initial state of the register bits are determined by the RXD_A and RXD_B input pins during power-up.
BYTE 8 - A-Channels Equalizer and Output Control (AEOC)
SELx_A: Equalizer configuration, Dx_A: Emphasis control, Sx_A: Output level control (see Configuration Table)
Bit
7
6
5
4
3
2
Name
SEL0_A SEL1_A SEL2_A
D0_A
D1_A
D2_A
Type
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
1
1
1
1
1
1
State
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
07-0277
9
1
S0_A
R/W
1
0
S1_A
R/W
1
PS8934A
01/21/08