PI2EQX5864 Datasheet, PDF (6/18 Pages) Pericom Semiconductor Corporation – 5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis, &I2C Control

PI2EQX5864
5.0Gbps 4-Lane PCI Express GenII Re-Driver
with Equalization, Emphasis and I²C Control
Loopback Operation
Each lane of the 5864 provides a loopback mode for test purposes which is controlled by a strapping pin and I2C register bit. The
LB# pin controls all lanes together. When this pin is high normal data mode is enabled. When LB# is low the loopback mode is
enabled. The figure below diagrams this operation. Loopback is not intended to be dynamically switched, and the normal system
application is to initialize to one configuration or the other.
The Loopback mode can also support mux/demux operation. Using I2C configuration, unused inputs and outputs can be disabled to
minimize power and unnecessary noise.
A0
A0
B0
B0
Normal Operation
LB#=0
A0
A0
B0
B0
Loopback Mode
LB#=1
A0
A0
B0
B0
A0
A0
B0
B0
Mux Function
ODIS_AO = 1
Solid: LB_A0B0#=1
Dashed: LB_A0B0#=0
Demux Function
INDIS_BO = 1
Solid: LB=0
Dashed: LB=1
I²C Operation
Loopback Modes
The 5806 I2C controller operates as a slave device, supporting standard rate operation of 100Kbps, with 7-bit addressing mode, with
support for offset byte-write and read. The data byte format is 8 bit bytes. The bytes must be accessed in sequential order from the
lowest to the highest byte with the ability to stop after any complete byte has been transferred. Address bits A4, A1 and A0 are pro-
grammable to support multiple chips environment. The data is loaded until a Stop sequence is issued.
Note that the I2C inputs, SCL and SDA operate at 1.2V logic levels and are 3.3V tolerant.
07-0277
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PS8934A
01/21/08