PI2EQX5864 Datasheet, PDF (3/18 Pages) Pericom Semiconductor Corporation – 5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis, &I2C Control

PI2EQX5864
5.0Gbps 4-Lane PCI Express GenII Re-Driver
with Equalization, Emphasis and I²C Control
54
RES_A#
I
24
RES_B#
I
50
RXD_A
I
22
RXD_B
I
53
52
55, 56, Center Pad
SCL
SDA
GND
1, 6, 11, 16, 21, 29, VDD
34, 39, 44, 49
I/O
I/O
PWR
PWR
DESCRIPTION of OPERATION
RES_A# is an active low channel reset input for Channel A0, A1, A2 and A3 with
internal 100K-Ohm pull-up resistor. When low, receiver detection cycle is reset,
and normal detection cycle is carry on after the pin goes high.
RES_B# is an active low channel reset input for Channel B0, B1, B2 and B3 with
internal 100K-Ohm pull-up resistor. When low, receiver detection cycle is reset,
and normal detection cycle is carry on after the pin goes high.
Receiver detect enable input for Channel A0, A1, A2 and A3 with internal 100K-
Ohm pull-up resistor.
Receiver detect enable input for Channel B0, B1, B2 and B3 with internal 100K-
Ohm pull-up resistor.
I²C SCL clock input. Up to 3.3V input tolerance.
I²C SDA data input. Up to 3.3V input tolerance
Supply Ground
1.2V Supply Voltage
Configuration Modes
Device configuration can be performed in two ways depending on the state of the MODE input. MODE determines whether IC
configuration status is from the input pins or via I2C control. When MODE is set high, the configuration input pins set the configura-
tion operating state as stored in configuration registers. While MODE is set high, changes to these control registers are disabled and
the initial condition is protected from any changes to insuring a known operating state. When the MODE pin is low, reprogramming
of these control registers via I2C is allowed. Note that the MODE pin is not latched, and is always active to enable or disable I2C
access.
During initial power-on, the value at the configuration input pins: LB#, RES_A#, RES_B#,RXD_A and RXD_B, will be latched to
the configuration registers as initial startup states.
Equalizer Configuration
The PI2EQX5864 input equalizer compensates for signal attenuation and Inter-Symbol Interference (ISI) resulting from long signal
traces or cables, vias, signal crosstalk and other factors, by boosting the gain of high-frequency signal components. Because either
too little, or too much, signal compensation may be non-optimal eight levels are provided to adjust for any application.
Equalizer configuration can be programmed via I²C when the mode pin is low. Each group of four channels, A and B, has separate
equalization control, and all four channels within the group are assigned the same configuration state. The Equalizer Selection table
below describes the register state and associated operation of the equalizer.
Equalizer Selection
SEL2_[A:B]
0
0
0
0
1
1
1
1
SEL1_[A:B]
0
0
1
1
0
0
1
1
SEL0_[A:B]
0
1
0
1
0
1
0
1
@1.25GHz
0.5dB
0.6dB
1.0dB
1.9dB
2.8dB
3.6dB
5.0dB
7.7dB
@2.5GHz
1.2dB
1.5dB
2.6dB
4.3dB
5.8dB
7.1dB
9.0dB
12.3dB
07-0277
3
PS8934A
01/21/08